XRT72L50 Datasheet, PDF (422/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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The Maintenance and Adaptation (ma) byte format
BIT 7
FERF
BIT 6
FEBE
BIT 5
BIT 4
Payload Type
BIT 3
BIT 2
BIT 1
Payload Dependent
BIT 0
Timing
Marker
This User-selectable number of E3 frames is either 3 or 5, depending upon the value that has been written into
Bit 4 (Rx FERF Algo) within the Rx E3 Configuration & Status Register, as depicted below.
RxE3 Configuration & Status Register 1 - (E3, ITU-T G.832) (Address = 0x10)
BIT 7
BIT 6
RxPLDType[2:0]
BIT 5
RO
RO
RO
0
0
0
BIT 4
RxFERF
Algo
R/W
0
BIT 3
RxTMark
Algo
R/W
0
BIT 2
BIT 1
RxPLDExp[2:0]
BIT 0
RO
RO
RO
0
0
0
Writing a “0” into this bit-field causes the Receive E3 Framer block to declare a FERF condition, if it detects 3
consecutive incoming E3 frames, that have the FERF bit (within the MA byte) set to “1”.
Writing a “1” into this bit-field causes the Receive E3 Framer block to declare a FERF condition, if it detects 5
consecutive incoming E3 frames, that have the FERF bit (within the MA byte) set to “1”.
Whenever the Receive E3 Framer block declares a FERF condition, then it will do the following.
• Generate a Change in FERF Condition interrupt to the MIcroprocessor. Hence, the Receive E3 Framer block
will assert Bit 3 (FERF Interrupt Status) within the Rx E3 Framer Interrupt Status register - 2, as depicted
below.
RxE3 Interrupt Status Register - 2 (Address = 0x13)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
0
BIT 5
Not Used
BIT 4
FEBE
Interrupt
Status
RO
RUR
0
0
BIT 3
FERF
Interrupt
Status
RUR
1
BIT 2
BIT 1
BIP-8
Error Interrupt
Status
Framing
Byte Error
Interrupt
Status
RUR
RUR
0
0
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
• Set the Rx FERF bit-field, within the Rx E3 Configuration/Status Register to “1”, as depicted below.
RxE3 Configuration & Status Register 2 (Address = 0x11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Rx LOF Algo RxLOF
RxOOF
RxLOS
RxAIS
R/W
RO
RO
RO
RO
0
0
0
0
0
BIT 2
RxPld Unstab
RO
0
BIT 1
Rx
TMark
RO
0
BIT 0
RxFERF
RO
1
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