XRT72L50 Datasheet, PDF (225/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Figure 75 presents a simple illustration of the Receive Overhead Data Output Interface block within the
XRT72L50.
FIGURE 75. THE RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK
RxOHFrame
RxOH
RxOHClk
RxOHEnable
Receive
Overhead Output
Interface Block
From Receive DS3
Framer Block
The DS3 frame consists of 4760 bits. Of these bits, 4704 bits are payload bits and the remaining 56 bits are
overhead bits. The XRT72L50 has been designed to handle and process both the payload type and overhead
type bits for each DS3 frame.
The Receive Payload Data Output Interface block, within the Receive Section of the XRT72L50, has been
designed to handle the payload bits. Likewise, the Receive Overhead Data Output Interface block has been
designed to handle and process the overhead bits.
The Receive Overhead Data Output Interface block unconditionally outputs the contents of all overhead bits
within the incoming DS3 data stream. The XRT72L50 does not offer the user a means to shut off this
transmission of data. However, the Receive Overhead Output Interface block does provide the user with the
appropriate output signals for external Data Link Layer equipment to sample and process these overhead bits,
via the following two methods.
• Method 1- Using the RxOHClk clock signal.
• Method 2 - Using the RxClk and RxOHEnable output signals.
Each of these methods are described below.
4.3.4.1 Method 1 - Using the RxOHClk Clock signal
The Receive Overhead Data Output Interface block consists of four (4) signals. Of these four signals, the
following three signals are to be used when sampling the DS3 overhead bits via Method 1.
• RxOH
• RxOHClk
• RxOHFrame
Each of these signals are listed and described below in Table 38.
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