XRT72L50 Datasheet, PDF (429/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
The Message Oriented Signaling (e.g., LAP-D) Processing via the Receive E3 HDLC Controller block
The LAPD Receiver (within the Receive E3 HDLC Controller block) allows the user to receive PMDL messages
from the remote terminal equipment, via the Inbound E3 frames. In this case, the Inbound message bits will be
carried by either the GC or the NR byte-fields within each E3 Frame. The remote LAPD Transmitter will
transmit a LAPD Message to the Near-End Receiver via either one of these bytes within each E3 Frame. The
LAPD Receiver will receive and store the information portion of the received LAPD frame into the Receive
LAPD Message Buffer, which is located at addresses: 0xDE through 0x135 within the on-chip RAM. The
LAPD Receiver has the following responsibilities.
• Framing to the incoming LAPD Messages
• Filtering out stuffed "0’s" (Between the two flag sequence bytes, 0x7E)
• Storing the Frame Message into the Receive LAPD Message Buffer
• Perform Frame Check Sequence (FCS) Verification
• Provide status indicators for
End of Message (EOM)
Flag Sequence Byte detected
Abort Sequence detected
Message Type
C/R Type
The occurrence of FCS Errors
The LAPD receiver's actions are facilitated via the following two registers.
• Rx E3 LAPD Control Register
• Rx E3 LAPD Status Register
Operation of the LAPD Receiver
The LAPD Receiver, once enabled, will begin searching for the boundaries of the incoming LAPD message.
The LAPD Message Frame boundaries are delineated via the Flag Sequence octets (0x7E), as depicted in
Figure 188.
FIGURE 188. LAPD MESSAGE FRAME FORMAT
Flag Sequence (8 bits)
SAPI (6-bits)
TEI (7 bits)
Control (8-bits)
C/R ^EA
EA
76 or 82 Bytes of Information (Payload)
FCS - MSB
FCS - LSB
Flag Sequence (8-bits)
Where: Flag Sequence = 0x7E
SAPI + CR + EA = 0x3C or 0x3E
TEI + EA = 0x01
Control = 0x03
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