XRT72L50 Datasheet, PDF (214/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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Hence, a given Terminal Equipment receiving a DS3 data stream can identify the framing format of this DS3
data stream, by reading the value fo the AIC bit-field. The Receive DS3 Framer block permits the user’s
Microcontroller/MIcroprocessor to determine the state of the AIC bit-field (within the incoming DS3 data
stream) by writing the value of the AIC bit-field, within the most recently received DS3 frame, into bit 3 (RxAIC)
within the Rx DS3 Status Register (Address = 0x11), as illustrated below.
RxDS3 Status Register (Address = 0x11)
BIT 7
RO
0
BIT 6
Reserved
RO
0
BIT 5
RO
0
BIT 4
RxFERF
RO
0
BIT 3
RxAIC
RO
0
BIT 2
RO
0
BIT 1
RxFEBE[2:0]
RO
0
BIT 0
RO
0
The Receive DS3 Framer block will also generate an interrupt if it detects a change of state in the AIC bit-field
(within the incoming DS3 data stream). If this occurs, then the Receive DS3 Framer block will set Bit 2 (AIC
Interrupt Status) within the Rx DS3 Interrupt Stauts Register (Address = 0x13) to “1” as illustrated below.
RxDS3 Interrupt Status Register (Address = 0x13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
AIC
Interrupt
Status
RUR
1
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
0
4.3.2.6 Performance Monitoring of the DS3 Transport Medium
The DS3 Frame consists of some overhead bits that are used to support performance monitoring of the DS3
Transmission Link. These bits are the P-Bits and the CP-Bits.
4.3.2.6.1
P-Bit Checking/Options
The remote Transmit DS3 Framer will compute the even parity of the payload portion of an outbound DS3
Frame and will place the resulting parity bit value in the 2 P-bit-fields within the very next outbound DS3 Frame.
The value of these two bits fields is expected to be the identical.
The Receive DS3 Framer block, while receiving each of these DS3 Frames (from the remote Transmit DS3
Framer), will compute the even-parity of the payload portion of the frame. The Receive DS3 Framer block will
then compare this locally computed parity value to that of the P-bit fields within the very next DS3 Frame. If the
Receive DS3 Framer block detects a parity error, then two things will happen:
1. The Receive DS3 Framer block will inform the µP/µC of this occurrence by generating a Detection of P-Bit
Error interrupt,
2. The Receive DS3 Framer block will alter the value of the FEBE bits, (to a pattern other than 111) that the
Near-End Transmit DS3 Framer will be transmitting back to the remote Terminal.
3. The XRT72L50 Framer IC will increment the PMON Parity Error Event Count Registers (Address = 0x54
and 0x55) for each detected parity error, in the incoming DS3 data stream. The bit-format of these two reg-
isters follows.
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