XRT72L50 Datasheet, PDF (70/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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1. When the Receive DS3/E3 Framer block first detects an AIS Condition in the incoming DS3 data stream,
and
2. When the Receive DS3/E3 Framer block has detected the end of an AIS Condition.
The local µP can determine the current state of the AIS condition by reading bit 7 of the Rx DS3 Configuration
and Status Register (Address = 0x10).
NOTE: For more information on the AIS Condition, refer to Section 4.3.2.5.2.
Bit 4 - Idle Interrupt Status
This Reset Upon Read bit-field is set to "1" when the Receive DS3/E3 Framer block detects a Change in the
Idle Condition in the incoming DS3 data stream. Specifically, the Receive DS3/E3 Framer block will assert this
bit-field under either of the following two conditions:
1. When the Receive DS3/E3 Framer block detects the onset of the Idle Condition and
2. When the Receive DS3/E3 Framer block detects the end of the Idle Condition.
The local µP can determine the current state of the Idle condition by reading bit 5 of the Rx DS3 Configuration
and Status Register (Address = 0x10).
NOTE: For more information into the Idle Condition, refer to Section 4.3.2.5.3.
Bit 3 - FERF Interrupt Status
This Reset Upon Read bit will be set to '1' if the Receive DS3/E3 Framer block has detected a Change in the
Rx FERF Condition, since the last time this register was read.
This bit-field will be asserted under either of the following two conditions.
1. When the Receive DS3/E3 Framer block first detects the occurrence of an Rx FERF Condition (all X-bits
are set to '0').
2. When the Receive DS3/E3 Framer block detects the end of the Rx FERF Condition (all X-bits are set to
'1').
The local microprocessor can determine the current state of the FERF Condition by reading bit 4, within the Rx
DS3 Status Register (Address = 0x11).
NOTE: For more information on the Rx FERF (Yellow Alarm) condition, refer to Section 4.3.2.5.4.
Bit 2 - (Change in) AIC Interrupt Status
This Reset Upon Read bit-field is set to "1" if the AIC bit-field, within the incoming DS3 frames, has changed
state since the last read of this register.
NOTE: For more information on this interrupt condition, refer to Section 4.3.2.5.6.
Bit 1 - OOF Interrupt Status
This Reset Upon Read bit-field is set to "1" if the Receive DS3/E3 Framer block has detected a Change in the
Out-of-Frame (OOF) Condition, since the last time this register was read. Therefore, this bit-field will be
asserted under either of the following two conditions:
1. When the Receive DS3/E3 Framer block has detected the appropriate conditions to declare an OOF Con-
dition.
2. When the Receive DS3/E3 Framer block has transitioned from the OOF Condition (Frame Acquisition
Mode) into the In-Frame Condition (Frame Maintenance mode).
NOTE: For more information of the OOF Condition, refer to Section 4.3.2.2.
Bit 0 - P-Bit Error Interrupt Status
This Reset Upon Read bit-field indicates whether or not the Detection of P-bit error interrupt has occurred
since the last read of this register. This bit-field will be "0" if the Detection of P-bit error interrupt has NOT
occurred since the last read of this register. This bit-field will be set to "1", if this interrupt has occurred since
the last read of this register. The Detection of P-bit Error interrupt will occur if the Receive DS3/E3 Framer
Block detects a P-bit error in the incoming DS3 frame.
NOTE: For more information into the role of P-bits, refer to Section 4.3.2.6.1.
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