XRT72L50 Datasheet, PDF (176/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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• Tx DS3 FEAC Register (Address = 0x32)
• Tx DS3 FEAC Configuration and Status Register (Address = 0x31)
Operating the Transmit FEAC Processor
To transmit a FEAC message to the remote terminal, the following steps must be executed.
STEP 1 - Write the six bit FEAC Codeword (to be sent)
In this step, the µP/µC writes the six bit FEAC code word into the Tx DS3 FEAC Register. The bit format of this
register is presented below.
Tx DS3 FEAC Register (Address = 0x32)
BIT 7
Not Used
RO
0
BIT 6
TxFEAC[5]
R/W
d5
BIT 5
TxFEAC[4]
R/W
d4
BIT 4
TxFEAC[3]
R/W
d3
BIT 3
TxFEAC[2]
R/W
d2
BIT2
TxFEAC[1]
R/W
d1
BIT 1
TxFEAC[0]
R/W
d0
BIT 0
Not Used
R0
0
STEP 2 - Enabling the Transmit FEAC Processor
To enable the Transmit FEAC Processor within the Transmit DS3 HDLC Controller block, a “1” must be written
into bit 2 (TxFEAC Enable) within the Tx DS3 FEAC Configuration and Status Register, as depicted below.
Transmit DS3 FEAC Configuration and Status Register (Address = 0x31)
BIT 7
Not Used
BIT 6
Not Used
BIT 5
Not Used
RO
RO
RO
x
x
x
BIT 4
TxFEAC
Interrupt
Enable
R/W
x
BIT 3
TxFEAC
Interrupt
Status
RUR
x
BIT2
TxFEAC
Enable
R/W
1
BIT 1
TxFEAC
Go
R/W
X
BIT 0
TxFEAC
Busy
R0
X
STEP 3 - Initiate the Transmission of the FEAC Message
The transmission of the FEAC code word residing in the Tx DS3 FEAC registe) can be initiated by writing a “1”
to bit 1 (TxFEAC Go) within the Tx DS3 FEAC Configuration and Status register, as depicted below.
Transmit DS3 FEAC Configuration and Status Register (Address = 0x31)
BIT 7
Not Used
BIT 6
Not Used
BIT 5
Not Used
RO
RO
RO
x
x
x
BIT 4
TxFEAC
Interrupt
Enable
R/W
x
BIT 3
TxFEAC
Interrupt
Status
RUR
x
BIT2
TxFEAC
Enable
R/W
1
BIT 1
TxFEAC
Go
R/W
1
BIT 0
TxFEAC
Busy
R0
X
While executing this particular write operation, the binary value, 000xx110b, should be written into the Tx DS3
FEAC Configuration and Status Register. This insures that a “1” is being written to Bit 2 (Tx FEAC Enable) of
the register to keep the Transmit FEAC Processor enabled.
Once this step has been completed, the Transmit FEAC Processor proceeds to transmit the 16 bit FEAC code
via the outbound DS3 frames. This 16 bit FEAC message must be transmitted repeatedly at least 10
consecutive times requiring a total of 160 DS3 Frames. During this process, Bit 0 (Tx FEAC Busy) is asserted
indicating that the Tx FEAC Processor is currently transmitting the FEAC Message to the remote Terminal.
This bit-field will toggle to "0" upon completion of the 10th transmission of the FEAC Code Message. The
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