XRT72L50 Datasheet, PDF (37/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
MAX. UNITS
CONDITIONS
t₅₁ Rising edge of RxClk to RxFrame output delay
13
ns DS3 Applications
16
ns E3 Applications
t₅₂ Rising edge of RxClk to RxOHInd output delay.
13
ns DS3 Applications
16
ns E3 Applications
Receive Payload Data Output Interface Timing - Nibble Mode Operation (see Figure 14)
t₅₃
Falling edge of RxClk to rising edge of RxFrame out-
put delay
2.1
ns
t₅₄
Falling edge of RxClk to rising edge of RxNib[3:0]
output delay
2
ns
Receive Overhead Data Output Interface Timing - Method 1 - Using RxOHClk (see Figure 15)
t_59A ^{Falling edge of RxOHClk to RxOHFrame output}
20
23
ns
DS3 Applications
25
t_59B ^{Falling edge of RxOHClk to RxOH output delay}
20
0
ns E3 Applications
23
ns DS3 Applications
25
0
ns E3 Applications
Receive Overhead Data Output Interface Timing - Method 2 - Using RxOHEnable (see Figure 16)
t₆₀ Rising edge of RxOutClk to rising edge of
2
9.4
ns
RxOHEnable delay.
t_60A Rising edge of RxOHFrame to rising edge of
RxOHEnable delay
88
ns ^{DS3 Applications}
224
ns ^{E3, ITU-T G.832}
Applications
t_60B RxOH Data Valid to rising edge of
RxOHEnable delay
28
ns ^{E3, ITU-T G.751}
Applications
88
ns ^{DS3 Applications}
85
ns ^{E3, ITU-T G.832}
Applications
Microprocessor Interface - Intel (See Figure 17)
t₆₄ CS Setup Time to ALE_AS Low
t₆₅ CS Hold Time from ALE_AS Low.
t₆₆ RD_DS, WR_R/W Pulse Width
Intel Type Read Operations (See Figure 17)
t₆₇ Data Valid from RD_DS Low.
t₆₈ Data Bus Floating from RD_DS High
t₆₉ CS to RD read or write Time
28
ns ^{E3, ITU-T G.751}
Applications
0
ns
1
ns
87
ns
32
ns
9
ns
3
ns
24