XRT72L50 Datasheet, PDF (245/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
If the Change of State on Receive FERF Interrupt is enabled, then the XRT72L50 Framer IC will generate an
interrupt in response to either of the following conditions.
1. When the XRT72L50 Framer IC detects the FERF indicator, in the incoming DS3 data stream, and
2. When the XRT72L50 Framer IC no longer detects the FERF indicator, in the incoming DS3 data stream.
Conditions causing the XRT72L50 Framer IC to declare an FERF (Far-End-Receive Failure) condition
• If the Receive DS3 Framer block (within the XRT72L50 Framer IC) detects some incoming DS3 frames with
both of the X bits set to “0”.
Conditions causing the XRT72L50 Framer IC to clear the FERF condition.
• Whenever, the Receive DS3 Framer block starts to detect some incoming DS3 frames, in which the X bits
are not set to “0”.
Enabling and Disabling the Change of State on Receive FERF Interrupt:
To enable or disable the Change of State on Receive FERF Interrupt, write the appropriate value into Bit 3
(FERF Interrupt Enable) within the RxDS3 Interrupt Enable Register, as illustrated below.
RxDS3 Interrupt Enable Register (Address = 0x12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
AIC
Interrupt
Enable
OOF
Interrupt
Enable
P-Bit Error
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Change of State on Receive FERF Interrupt
Whenever the XRT72L50 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request Output pin (Int) by driving it "High".
• It will set Bit 3 (FERF Interrupt Status), within the Rx DS3 Interrupt Status Register, to “1”, as indicated
below.
RxDS3 Interrupt Status Register (Address = 0x13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
1
BIT 2
AIC
Interrupt
Status
RUR
0
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters a Change in FERF Condition on Receive Interrupt, it should do
the following.
1. It should determine the current state of the FERF condition. Recall, that this interrupt can generated,
whenever the XRT72L50 Framer declares or clears the FERF condition. Hence, to determine the current
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