XRT72L50 Datasheet, PDF (430/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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The 16 bit FCS is calculated using CRC-16, x16 + x12 + x5 + 1
The first byte of the information or payload field indicates the type and size of the message being transferred.
The value of this information field and the corresponding message type/size follow:
CL Path Identification = 0x38 (76 bytes)
IDLE Signal Identification = 0x34 (76 bytes)
Test Signal Identification = 0x32 (76 bytes)
ITU-T Path Identification = 0x3F (82 bytes)
Enabling and Configuring the LAPD Receiver
Before the LAPD Receiver can begin to receive and process incoming LAPD Message frames, the user must
do two things.
1. The byte-field within each E3 frame which will be carrying the comprising octets of the LAPD Message
frame must be specified and
2. The LAPD Receiver must be enabled.
Each of these steps are discussed in detail below.
1. Specifying which byte-field, within each E3 frame, will be carrying the LAPD Message frame.
The LAPD Receiver can receive the LAPD Message frame octets via either the GC-byte-field or the NR-byte-
field, within each incoming E3 frame. The user makes this selection by writing the appropriate bit to Bit 3 (DL
from NR) within the Rx E3 LAPD Control Register, as depicted below.
RxE3 LAPD Control Register (Address = 0x18)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
DL from NR
BIT 2
RxLAPD
Enable
R/W
R/W
0
0
BIT 1
RxLAPD
Interrupt
Enable
R/W
1
BIT 0
RxLAPD
Interrupt
Status
RUR
0
Writing a “0” into this bit-field causes the LAPD Receiver to read in the octets from the GC byte-field of each E3
frame and with these octets, reassembling the LAPD Message frame. Writing a “1” into this bit-field causes the
LAPD Receiver to receive the LAPD Message frame octets from the NR byte-field of each E3 frame.
2. Enabling the LAPD Receiver
The LAPD Receiver must be enabled before it can begin receiving and processing any LAPD Message frames.
The LAPD Receiver can be enabled by writing a “1” to Bit 2 (RxLAPD Enable) of the Rx E3 LAPD Control
Register, as indicated below.
RxE3 LAPD Control Register (Address = 0x18)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
DL from NR
BIT 2
RxLAPD
Enable
R/W
R/W
0
1
BIT 1
RxLAPD
Interrupt
Enable
R/W
1
BIT 0
RxLAPD
Interrupt
Status
RUR
0
Once the LAPD Receiver has been enabled, it will begin searching for the Flag Sequence octet (0x7E), in
either the GC or the NR byte-fields within each incoming E3 frame. When the LAPD Receiver finds the flag
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