XRT72L50 Datasheet, PDF (329/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE 131. FLOW CHART DEPICTING THE FUNCTIONALITY OF THE LAPD RECEIVER
START
Enable the LAPD Receiver
This is done by writing the value 0xFC into
the RxLAPD Control Register (Adress =
0x18)
LAPD Receiver begins reading in the N
bits from each inbound E3 fram e.
Does
LAPD Receiver
detect
6 Consecutive
"O ne s"?
Destuff "Zeros"
NO
after any 5
C o n s e c u tiv e
"O ne s"
YES
Receive LAPD
Message
1
1
W rite
0x7E
to
0xDE
First Flag
Sequence is
R ec eive d
NO
Has first
Flag Sequence
been received?
NO
YES
YES
ABORT
Does
LAPD Receiver
detect
7 Consecutive
"O ne s"?
Does
LAPD Receiver
detect
6 Consecutive
"O ne s"?
Resart
search for
First Flag
Sequence
YES
1
Does
LAPD Receiver
detect
YES
7 Consecutive
"O ne s"?
Execute LAPD
R ec eiv e d
1
Interrupt
Service
R outine
FCS error
bit "High"
NO
Is FCS
verifiy
OK?
YES
G e n e ra te
LAPD
R ec eiv e r
interrupt
1
NO
End of Message
W rite Received
LAPD Message
to Message Buffer
(0xDF thru 0x135)
Compute &
Verify FCS
based on
m essage length
by m essage type
5.3.4 The Receive Overhead Data Output Interface
Figure 132 presents a simple illustration of the Receive Overhead Data Output Interface block within the
XRT72L50.
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