XRT72L50 Datasheet, PDF (313/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Additionally, the Receive E3 Framer block will inform the external circuitry of its transition to the In-Frame state
by toggling both the RxOOF and RxLOF output pins "Low”.
Finally, the Receive E3 Framer block will negate both the RxOOF and the RxLOF bit-fields within the Rx E3
Configuration & Status Register, as depicted below.
RxE3 Configuration & Status Register - 2 (Address = 0x11)
BIT 7
RxLOF
Algo
R/W
0
BIT 6
RxLOF
RO
0
BIT 5
RxOOF
RO
0
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
0
BIT 2
BIT 1
Not Used
RO
RO
X
X
BIT 0
RxFERF
RO
X
When the Receive E3 Framer block is operating in the In-Frame state, it will then begin to perform Frame
Maintenance operations, where it will continue to verify that the Frame Alignment signal (FAS pattern) is
present, and at its proper location. While the Receive E3 Framer block is operating in the Frame Maintenance
Mode, it will declare an Out-of-Frame (OOF) Condition if it detects an invalid FAS pattern in four consecutive
frames.
Since the Receive E3 Framer block requires the detection of an invalid FAS pattern in four consecutive frames,
in order for it to transition to the OOF Condition state, it can tolerate some errors in the Framing Alignment
bytes, and still remain in the In-Frame state. However, each time the Receive E3 Framer block detects an error
in the FAS pattern, it will increment the PMON Framing Error Event Count Registers (Address = 0x52 and
0x53). The bit-format for these two registers are depicted below.
PMON Framing Bit/Byte Error Count Register - MSB (Address = 0x52)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Framing Bit/Byte Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
PMON Framing Bit/Byte Error Count Register - LSB (Address = 0x53)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
BIT 4
BIT 3
BIT 2
Framing Bit/Byte Error Count - Low Byte
RUR
RUR
RUR
RUR
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
5.3.2.3 Forcing a Reframe via Software Command
The XRT72L50 Framer IC permits the user to command a reframe procedure with the Receive E3 Framer
block via software command. If the user writes a “1” into Bit 0 (Reframe) within the I/O Control Register
(Address = 0x01), as depicted below, then the Receive E3 Framer block will be forced into the FAS Pattern
Search state, per Figure 126, and will begin its search for the FAS Pattern.
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