XRT72L50 Datasheet, PDF (324/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 130. LAPD MESSAGE FRAME FORMAT
Flag Sequence (8 bits)
SAPI (6-bits)
TEI (7 bits)
Control (8-bits)
C/R EA
EA
76 or 82 Bytes of Information (Payload)
FCS - MSB
FCS - LSB
Flag Sequence (8-bits)
Where: Flag Sequence = 0x7E
SAPI + CR + EA = 0x3C or 0x3E
TEI + EA = 0x01
Control = 0x03
The 16 bit FCS is calculated using CRC-16, x16 + x12 + x5 + 1
The first byte of the information field indicates the type and size of the message being transferred. The value of
this information or payload field and the corresponding message type/size follow:
CL Path Identification = 0x38 (76 bytes)
IDLE Signal Identification = 0x34 (76 bytes)
Test Signal Identification = 0x32 (76 bytes)
ITU-T Path Identification = 0x3F (82 bytes)
Enabling and Configuring the LAPD Receiver
Before the LAPD Receiver can begin to receive and process incoming LAPD Message frames, the user must
do two things.
1. Enabling the LAPD Receiver
The LAPD Receiver must be enabled before it can begin receiving and processing any LAPD Message frames.
The LAPD Receiver can be enabled by writing a “1” to Bit 2 (RxLAPD Enable) of the Rx E3 LAPD Control
Register, as indicated below.
)
RxE3 LAPD Control Register (Address = 0x18
BIT 7
RO
0
BIT 6
BIT 5
Not Used
BIT 4
RO
RO
RO
0
0
0
BIT 3
RO
0
BIT 2
RxLAPD
Enable
R/W
1
BIT 1
BIT 0
RxLAPD
RxLAPD
Interrupt Enable Interrupt Status
R/W
RUR
0
0
Once the LAPD Receiver has been enabled, it will begin searching for the Flag Sequence octet (0x7E), in the
N bit-fields within each incoming E3 frame. When the LAPD Receiver finds the flag sequence byte, it will
assert the Flag Present bit (Bit 0) within the Rx E3 LAPD Status Register, as depicted below.
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