XRT72L50 Datasheet, PDF (404/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 171. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND
TXNEG ARE CONFIGURED TO BE UPDATED ON THE RISING EDGE OF TXLINECLK
t32
TxLineClk
t30
t33
TxPOS
TxNEG
FIGURE 172. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND
TXNEG ARE CONFIGURED TO BE UPDATED ON THE FALLING EDGE OF TXLINECLK
t32
TxLineClk
t31
t33
TxPOS
TxNEG
6.2.6 Transmit Section Interrupt Processing
The Transmit Section of the XRT72L50 can generate an interrupt to the Microprocessor/Microcontroller for the
following reasons.
• Completion of Transmission of LAPD Message
6.2.6.1 Enabling Transmit Section Interrupts
The Interrupt Structure within the XRT72L50 contains two hierarchical levels:
• Block Level
• Source Level
The Block Level
The Enable State of the Block Level for the Transmit Section Interrupts dictates whether or not interrupts
(enabled) at the source level, are actually enabled.
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