XRT72L50 Datasheet, PDF (163/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
The Terminal Equipment serially outputs the data on the DS3_Data_Out[3:0] pins upon the rising edge of the
signal at the DS3_Clock_In input pin. The XRT72L50 latches the data residing on the TxNib[3:0] input pins on
the rising edge of the TxNibClk signal.
In this case, the XRT72L50 provides the framing reference signal by pulsing the TxFrame output pin and in
turn, the Tx_Start_of_Frame input pin of the Terminal Equipment "High" for one nibble-period coincident with
the last nibble within a given DS3 frame.
Finally, the XRT72L50 always internally generates the Overhead bits when it is operating in both the DS3 and
Nibble-parallel modes. The XRT72L50 pulls the TxOHInd input pin "Low".
The behavior of the signals between the XRT72L50 and the Terminal Equipment for DS3 Mode 6 Operation is
illustrated in Figure 43.
FIGURE 43. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L50 AND THE TERMINAL
EQUIPMENT (DS3 MODE 6 OPERATION)
Terminal Equipment Signals
TxInClk
DS3_Nib_Clock_In
DS3_Data_Out[3:0]
Tx_Start_of_Frame
Nibble [1175]
Nibble [0]
XRT72L5x Transmit Payload Data I/F Signals
TxInClk
TxNibClk
TxNib[3:0]
TxNibFrame
Nibble [1175]
Nibble [0]
DS3 Frame Number N DS3 Frame Number N + 1
Note: TxNibFrame pulses high to denote
DS3 Frame Boundary.
Sampling Edge of the XRT72L5x Device
How to configure the XRT72L50 into Mode 6
1. Set the NibIntf input pin "High".
2. Set the TimRefSel[1:0] bit-fields within the Framer Operating Mode Register to “1X” as illustrated below.
Framer Operating Mode Register (Address = 0x00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
Local Loop-back DS3/E3 Internal LOS RESET
Enable
R/W
R/W
R/W
R/W
0
0
1
0
Interrupt
Enable Reset
R/W
1
Frame Format
R/W
0
3. Interface the XRT72L50 to the Terminal Equipment, as illustrated in Figure 42.
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
1
x
150