XRT72L50 Datasheet, PDF (88/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
2.3.3.25 Receive E3 TTB-14 Register (E3, ITU-T G.832)
RxE3 TTB-14 Register (Address = 0x2A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RxTTB-14
RO
RO
RO
RO
RO
0
0
0
0
0
BIT 2
RO
0
áç
BIT 1
RO
0
BIT 0
RO
0
This Read-Only register contains the fifteenth (15th) byte within the 16 byte Trail Trace Buffer Message, that
has been received from the Remote Terminal. This register typical contains an ASCII character that is required
for the E.164 numbering format.
NOTE: For more information on the use of this register, refer to Section 6.3.2.9.
2.3.3.26 Receive E3 TTB-15 Register (E3, ITU-T G.832)
RxE3 TTB-15 Register (Address = 0x2B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxTTB-15
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This Read-Only register contains the sixteenth (16th) byte within the 16 byte Trail Trace Buffer Message, that
has been received from the Remote Terminal. This register typical contains an ASCII character that is required
for the E.164 numbering format.
NOTE: For more information on the use of this register, refer to Section 6.3.2.9.
2.3.3.27 Receive E3 Framer SSM Register (E3, ITU-T G.832)
RxE3 ssm Register (Address = 0x2C)
BIT 7
RxSSM
Enable
BIT 6
BIT 5
MFI[1:0]
BIT 4
Reserved
BIT 3
BIT 2
BIT 1
RxSSM[3:0]
BIT 0
R/W
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
Bit 7 - RxSSM Enable
This Read/Write bit-field permits the user to configure the Receive Section of a given channel to support
processing of the MA byte via either the old or the new ITU-T G.832 Framing format.
Setting this bit-field to “1” configures the Receive Section to support the new E3, ITU-T G.832 framing standard
(October 1998 Revision). Setting this bit-field to “0” configures the Receive Section to support the old E3, ITU-
T G.832 framing standard (November 1995).
Bits 6, 5 - MF[1:0] - SSM Multiframe Indicator Bits
These two bits reflect the states of the SSM Multi-frame phase indicators, within the most recently received E3
frame. Stated another ways, these two bit-fields reflect Bits 2 and 1 within the MA byte, in the most recently
received E3 frame.
NOTE: These two bit-fields are only valid if the Receive Section of the Channel has been configured to support the October
1998 Revision of the ITU-T G.832 Framing format for E3.
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