XRT72L50 Datasheet, PDF (273/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE 44: A LISTING OF THE OVERHEAD BITS WITHIN THE E3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN THE
XRT72L50 IC
OVERHEAD BIT
FAS Signal - Bit 9
FAS Signal - Bit 8
FAS Signal - Bit 7
FAS Signal - Bit 6
FAS Signal - Bit 5
FAS Signal - Bit 4
FAS Signal - Bit 3
FAS Signal - Bit 2
FAS Signal - Bit 1
FAS Signal - Bit 0
A Bit
N Bit
INTERNALLY GENERATED
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ACCESSIBLE VIA THE TRANSMIT OVERHEAD
DATA INPUT INTERFACE
No
No
No
No
No
No
No
No
No
No
Yes
Yes
BUFFER/REGISTER
ACCESSIBLE
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NOTES:
1. The XRT72L50 contains mask register bits that permit the user to alter the state of the internally generated value
for these bits.
2. The Transmit LAPD Controller/Buffer can be configured to be the source of the N bits, within the outbound E3 data
stream.
The Transmit Overhead Data Input Interface permits the user to insert overhead data into the outbound E3
frames via the following two different methods.
• Method 1 - Using the TxOHClk clock signal
• Method 2 - Using the TxInClk and the TxOHEnable signals.
Each of these methods are described below.
5.2.2.1 Method 1 - Using the TxOHClk Clock Signal
The Transmit Overhead Data Input Interface consists of the five signals. Of these five (5) signals, the following
four (4) signals are to be used when implementing Method 1.
• TxOH
• TxOHClk
• TxOHFrame
• TxOHIns
Each of these signals are listed and described below.
Table 45.
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