XRT72L50 Datasheet, PDF (427/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
PMON Parity Error Count Register - LSB (Address = 0x55)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
Parity Error Count - Low Byte
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
The user can determine the number of BIP-8 Errors that have been detected by the Receive E3 Framer block,
since the last read of these registers. These registers are reset-upon-read.
6.3.2.8 Processing of the Far-End-Block Error (FEBE) Bit-fields
Whenever the Receive E3 Framer detects an error in the incoming E3 frame, via EM byte verification, it will
inform the Local Transmit E3 Framer of this fact. The Local Transmit E3 Framer will, in turn, notify the Remote
Terminal (e.g., the source of the errored E3 frame) by transmitting an E3 frame, with the FEBE bit-field (within
the MA byte) set to “1”.
If the Receive E3 Framer receives any E3 frame, with the FEBE bit-field set to “1”, then it will do the following.
• It will generate a FEBE Event interrupt to the Microprocessor/Microcontroller. Hence, the Receive E3 Framer
block will set bit 4 (FEBE Interrupt Status) within the Rx E3 Framer Interrupt Status Register - 2, as depicted
below.
RxE3 Interrupt Status Register - 2 (Address = 0x15)
BIT 7
BIT 6
BIT 5
Not Used TTB Change Not Used
Interrupt Status
RO
RUR
RO
0
0
0
BIT 4
FEBE Inter-
rupt Status
RUR
1
BIT 3
BIT 2
BIT 1
BIT 0
FERF Inter- BIP-8 Error Framing Byte RxPld Mis
rupt
Interrupt Status Error Interrupt _{Interrupt Sta-}
Status
Status
tus
RUR
RUR
RUR
RUR
0
0
0
0
• Increment the PMON Received FEBE Event Count register - MSB/LSB, which is located at 0x56 and 0x57 in
the Framer Address space. The byte-format of these registers are presented below.
PMON FEBE Event Count Register - MSB (Address = 0x56)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FEBE Event Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
PMON FEBE Event Count Register - LSB (Address = 0x57)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
FEBE Event Count - Low Byte
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
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