XRT72L50 Datasheet, PDF (357/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE 144. THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK
TxOH_Ind
TxSer
TxNib[3:0]
TxInClk
TxNibClk
TxNibFrame
TxFrame
TxFrameRef
Transmit
Payload Data
Input Interface
Block
To Transmit E3
Framer Block
Each of the input and output pins of the Transmit Payload Data Input Interface are listed in Table 67 and
described below. The exact role that each of these inputs and output pins assume, for a variety of operating
scenarios are described throughout this section.
TABLE 67: LISTING AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT
INTERFACE
SIGNAL NAME
TxSer
TxNib[3:0]
TxInClk
TYPE
DESCRIPTION
Input
Transmit Serial Payload Data Input Pin:
If the user opts to operate the XRT72L50 in the serial mode, then the Terminal Equipment is
expected to apply the payload data (that is to be transported via the Outbound E3 data stream)
to this input pin. The XRT72L50 will sample the data that is at this input pin upon the rising
edge either the RxOutClk or the TxInClk signal (whichever is appropriate).
NOTE: This signal is only active if the NibIntf input pin is pulled "Low".
Input
Transmit Nibble-Parallel Payload Data Input pins:
If the user opts to operate the XRT72L50 in the Nibble-Parallel mode, then the Terminal Equip-
ment is expected to apply the payload data (that is to be transported via the Outbound E3 data
stream) to these input pins. The XRT72L50 will sample the data that is at these input pins upon
the rising edge of the TxNibClk signal.
NOTE: These pins are only active if the NibIntf input pin is pulled "High".
Input
Transmit Section Timing Reference Clock Input pin:
The Transmit Section of the XRT72L50 can be configured to use this clock signal as the Timing
Reference. If the user has made this configuration selection, then the XRT72L50 will use this
clock signal to sample the data on the TxSer input pin.
NOTE: If this configuration is selected, then a 34.368 MHz clock signal must be applied to this
input pin.
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