XRT72L50 Datasheet, PDF (301/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
If the Transmit Section is enabled (for interrupt generation) at the block level, then a given interrupt will be
enabled if it is also enabled at the source level. Conversely, if the Transmit Section is enabled (for interrupt
generation) at the Block level, then a given interrupt will still be disabled, if it is disabled at the source level.
As mentioned earlier, the Transmit Section of the XRT72L50 Framer IC contains the Completion of
Transmission of LAPD Message Interrupt.
The Enabling/Disabling and Servicing of this interrupt is presented below.
5.2.6.1.1
The Completion of Transmission of the LAPD Message Interrupt
If the Transmit Section interrupts have been enabled at the Block level, then the user can enable or disable the
Completion of Transmission of a LAPD Message Interrupt, by writing the appropriate value into Bit 1 (TxLAPD
Interrupt Enable) within the Tx E3 LAPD Status & Interrupt Register (Address = 0x34), as illustrated below.
TxE3 LAPD Status and Interrupt Register (Address = 0x34)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
TXDL Start
BIT 2
TXDL Busy
R/W
RO
0
0
BIT 1
TxLAPD
Interrupt
Enable
R/W
X
BIT 0
TxLAPD
Interrupt
Status
RUR
0
Setting this bit-field to “1’ enables the Completion of Transmission of a LAPD Message Interrupt. Conversely,
setting this bit-field to “0” disables the Completion of Transmission of a LAPD Message interrupt.
5.2.6.1.2
Servicing the Completion of Transmission of a LAPD Message Interrupt
As mentioned previously, once the user commands the LAPD Transmitter to begin its transmission of a LAPD
Message, it will do the following.
1. It will compute the FCS (Frame Check Sequence) value over the contents of 0x86 through 0xDB and
append this 16 bit value to the back-end of the user-message.
2. It will parse through the contents of the Transmit LAPD Message Buffer (located at address locations 0x86
through 0xDB and the FCS bytes) and search for a string of five (5) consecutive “1’s”. If the LAPD Trans-
mitter finds a string of five consecutive “1’s” (within the content of the LAPD Message Buffer, then it will
insert a “0” immediately after this string. (Except at 0x86 which should contain the flag sequence byte
0x7E.)
3. It will append a trailing flag sequence byte, 0x7E.
4. Finally, it will begin transmitting the contents of this LAPD Message frame via the N bits, within each out-
bound E3 frame.
5. Once the LAPD Transmitter has completed its transmission of this LAPD Message frame (to the Remote
Terminal Equipment), the XRT72L50 Framer IC will generate the Completion of Transmission of a LAPD
Message Interrupt to the Microcontroller/Microprocessor. Once the XRT72L50 Framer IC generates this
interrupt, it will do the following.
• Assert the Interrupt Output pin (Int) by toggling it "Low".
• Set Bit 0 (TxLAPD Interrupt Status) within the TxE3 LAPD Status and Interrupt Register, to “1” as illustrated
below.
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