XRT72L50 Datasheet, PDF (157/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Nibble-Parallel Mode
The XRT72L50 accepts the DS3 payload data from the Terminal Equipment in a nibble-parallel manner via the
TxNib[3:0] input pins. The Transmit Terminal Equipment Input Interface block latches this data into its circuitry
on the rising edge of the TxNibClk output signal.
Delineation of the outbound DS3 frames
The XRT72L50 pulses the TxNibFrame output pin "High" for one bit-period coincident with the XRT72L50
processing the last nibble of a given DS3 frame.
Sampling of payload data from the Terminal Equipment
In Mode 4, the XRT72L50 samples the data at the TxNib[3:0] input pins on the third rising edge of the
RxOutClk clock signal following a pulse in the TxNibClk signal (see Figure 39).
The TxNibClk signal from the XRT72L50 operates nominally at 11.184 MHz (e.g., 44.736 MHz divided by 4).
However, TxNibClk effectively operates at a Low clock frequency. The Transmit Payload Data Input Interface is
only used to accept the payload data which is intended to be carried by outbound DS3 frames. The Transmit
Payload Data Input Interface is not designed to accommodate the entire DS3 data stream.
The DS3 Frame consists of 4704 payload bits or 1176 nibbles. Therefore, the XRT72L50 supplies 1176
TxNibClk pulses between the rising edges of two consecutive TxNibFrame pulses. The DS3 Frame repetition
rate is 9.398kHz. Hence, 1176 TxNibClk pulses for each DS3 frame period amounts to TxNibClk running at
approximately 11.052 MHz. The method by which the 1176 TxNibClk pulses are distributed throughout the
DS3 frame period is presented below.
Nominally, the Transmit Section within the XRT72L50 will generate a TxNibClk pulse for every 4 RxOutClk or
TxInClk periods. However, in 14 cases within a DS3 frame period, the Transmit Payload Data Input Interface
allows 5 TxInClk periods to occur between two consecutive TxNibClk pulses.
Interfacing the Transmit Payload Data Input Interface block of the XRT72L50 to the Terminal Equipment
for Mode 4 Operation
This is illustrated in Figure 38
FIGURE 38. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK FOR MODE 4 (NIBBLE-PARALLEL/LOOP-TIMED) OPERATION
DS3_Nib_Clock_In
DS3_Data_Out[3:0]
Tx_Start_of_Frame
11.184MHz
4
VCC
TxNibClk
TxNib[3:0]
TxNibFrame
RxLineClk
NibIntf
44.736MHz
Terminal Equipment
DS3 Framer
144