XRT72L50 Datasheet, PDF (124/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
2.3.8.13 PMON Holding Register
PMON Holding Register (Address = 0x6C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PMON Holding Value
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
RUR
0
áç
BIT 1
RUR
0
BIT 0
RUR
0
Each of the above-defined PMON registers are 16 bit Reset-upon-Read registers. However, the bi-drectional
data bus (of the Framer IC) is only 8-bits wide. As a consequence, whenever the Microprocessor intends to
read a PMON register, there are two things to bear in mind.
1. This Microprocessor is going to require two read accesses in order read out the full 16-bit expression of
these PMON registers.
2. The entire 16-bit expression (of a given PMON register) is going to be reset to 0x0000, immediately after
the Microprocessor has completed its first read access to the PMON register.
Hence, the contents of the other byte (of the partially read PMON register) will reside within the PMON Holding
register.
2.3.8.14 One-Second Error Status Register
One-Second Error Status Register (Address = 0x6D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Errored
Second
Severely
Errored
Second
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
Bit 1 - Errored Second
This bit field indicates whether or not an error has occurred within the last One-Second accumulation interval.
This bit-field will be set to “1” if at least one error has occurred during the last One-Second accumulation
interval. Conversely, this bit-field will be set to "0" if no errors has occurred during the last one-second
accumulation interval.
Bit 0 - Severely Errored Second
This bit-field indicates whether or not the error rate in the last one-second interval was greater than 1 in 1000.
A "0" indicates that the error rate did not exceed 1 in 1000 in the last One-Second interval.
2.3.8.15 One-Second Line Code Violation Accumulator Register - MSB
LCV - One-Second Accumulator Register - MSB (Address = 0x6E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LCV - One-Second Count - High Byte
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This Read-Only register, along with the LCV - One-Second Accumulator Register - LSB (Address = 0x6F)
contains a 16-bit representation of the number of LCV (Line Code Violation) Events that have been detected by
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