XRT72L50 Datasheet, PDF (76/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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consecutive E3 frames, that each contain less than seven (7) "0’s" . If this bit-field is set to "1", then the
Receive DS3/E3 Framer block has declared, and is continuing to experience an AIS condition. If this bit-field is
set to "0", then the Receive DS3/E3 Framer block is currently not experiencing an AIS condition.
Bit 2 - RxPLDType UnStab
This Read-Only bit-field indicates whether or not the Receive DS3/E3 Framer block has been receiving a
consistent Payload Type value (within the MA Byte-Field) in the last 5 consecutive incoming E3 frames.
If the Receive DS3/E3 Framer block has detected a change in the Payload Type value, within the last 5
incoming E3 frames, then it will set this bit-field to "1". If the Payload Type value has been consistent in the last
5 E3 frames, then the Receive DS3/E3 Framer block will set this bit-field to "0".
Bit 1 - Rx TMark
This Read-Only bit-field reflects the most recently validated Timing Marker value. The Receive DS3/E3 Framer
block will validate the Timing Marker state, after it has detected a user-selectable number of consecutive
incoming E3 frames with a consistent Timing Marker value. The user makes this selection by writing the
appropriate value to Bit 3 (RxTMarkAlgo) within the Rx E3 Configuration/Status Register 1 (Address = 0x10).
Bit 0 - RxFERF (Far End Receive Failure)
This Read-Only bit-field indicates whether or not the Receive DS3/E3 Framer block is experiencing an FERF
(Far-End-Receive-Failure) condition. The Receive DS3/E3 Framer block will declare a FERF condition, if it has
received a user-selectable number of consecutive E3 frames, with the FERF bit-field (within the MA byte) set to
"1". This user-selectable number is either 3 or 5 E3 frames. Conversely, the Receive E3 Framer will negate
the FERF declaration, if it has received this user-selectable number of consecutive E3 frames, with the FERF
bit-field set to "0".
If this bit-field is set to "1", then the Receive DS3/E3 Framer block has declared an FERF condition. If this bit-
field is set to "0", then the Receive DS3/E3 Framer block has not declared an FERF condition.
NOTE: See Section 6.1.1.4, for a more detailed discussion on the meaning of the FERF bit-field, within the E3 frame.
2.3.3.3 Receive E3 Interrupt Enable Register 1 (E3, ITU-T G.832)
RxE3 Interrupt Enable Register 1 (Address = 0x12)
BIT 7
Not Used
BIT 6
SSM MSG
Interrupt
Enable
BIT 5
SSM OOS
Interrupt
Enable
BIT 4
COFA
Interrupt
Enable
BIT 3
OOF
Interrupt
Enable
BIT 2
LOF
Interrupt
Enable
BIT 1
LOS
Interrupt
Enable
BIT 0
AIS
Interrupt
Enable
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 6 - SSM Message Interrupt Enable
This Read/Write bit-field permits the user to enable or disable the Change in Synchronous Status Message
(SSM) interrupt. Setting this bit-field to “1” enables this interrupt. Setting this bit-field to “0” disables this
interrupt.
NOTE: This bit-field is ignored if the Channel is configured to support the November 1995 revision of the ITU-T G.832
Framing format for E3. (See Section 2.3.3.27.)
Bit 5 - SSM OOS (Out of Sequence) Interrupt Enable
This Read/Write bit-field permits the user to enable or disable the Change in SSM Out of Sequence State
interrupt. Setting this bit-field to “1” enables this interrupt. Setting this bit-field to “0” disables this interrupt.
NOTE: This bit-field is ignored if the Channel is configured to support the November 1995 revision of the ITU-T G.832
Framing format for E3. (See Section 2.3.3.27)
Bit 4 - Change of Frame Alignment (COFA) Interrupt Enable
This Read/Write bit-field allows the user to enable or disable the Change of Frame Alignment interrupt. Setting
this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
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