XRT72L50 Datasheet, PDF (421/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
• Generate the Change in AIS Condition Interrupt to the Microprocessor. Hence, the Receive E3 Framer block
will assert Bit 0 (AIS Interrupt Status) within the Rx E3 Framer Interrupt Status register - 1, as depicted
below.
RxE3 Interrupt Status Register - 1 (Address = 0x14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
LOF
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
RO
RO
RO
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
1
• Assert the RxAIS output pin.
• Set Bit 3 (Rx AIS) within the Rx E3 Configuration & Status Register, as depicted below.
RxE3 Configuration & Status Register 2 (Address = 0x11)
BIT 7
Rx LOF Algo
BIT 6
RxLOF
R/W
RO
0
0
BIT 5
RxOOF
RO
0
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
1
BIT 2
RxPld Unstab
RO
0
BIT 1
Rx
TMark
RO
0
BIT 0
RxFERF
RO
0
Clearing the AIS Condition
The Receive E3 Framer block will clear the AIS condition when it detects two consecutive E3 frames, with eight
or more zeros in the incoming data stream. The Receive E3 Framer block will inform the Microprocessor that
the AIS Condition has been cleared by:
• Generating the Change in AIS Condition Interrupt to the Microprocessor. Hence, the Receive E3 Framer
block will assert Bit 0 (AIS Interrupt Status) within the Rx E3 Framer Interrupt Status Register - 1.
• Clearing the RxAIS output pin (e.g., toggling it "Low”).
• Setting the RxAIS bit-field, within the Rx E3 Configuration & Status Register to “0”, as depicted below.
RxE3 Configuration & Status Register 2 (Address = 0x11)
BIT 7
Rx LOF Algo
BIT 6
RxLOF
R/W
RO
0
0
BIT 5
RxOOF
RO
0
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
0
BIT 2
RxPld Unstab
RO
0
BIT 1
Rx
TMark
RO
0
BIT 0
RxFERF
RO
0
6.3.2.6.3
The Far-End-Receive Failure (FERF) Condition
Declaring the FERF Condition
The Receive E3 Framer block will declare a Far-End Receive Failure (FERF) condition if it detects a user-
selectable number of consecutive incoming E3 frames, with the FERF bit-field (Bit 7, within the MA Byte) set to
“1”. Recall, the bit-format of the MA byte is presented below.
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