XRT72L50 Datasheet, PDF (433/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Receiver will know the type of size of the newly received PMDL Message. The LAPD Receiver will then reflect
this information in Bits 4 and 5 (RxLAPDType[1:0]) within the Rx E3 LAPD Status Register, as depicted below.
RxE3 LAPD Status Register (Address = 0x19)
BIT 7
Not Used
BIT 6
Rx ABORT
BIT 5
BIT 4
RxLAPDType[1:0]
BIT 3
RxCR
Type
BIT 2
RxFCS
Error
BIT 1
End of
Message
BIT 0
Flag
Present
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
Table 83 presents the relationship between the contents of RxLAPDType[1:0] and the type of message
received by the LAPD Receiver.
TABLE 83: THE RELATIONSHIP BETWEEN THE CONTENTS OF RXLAPDTYPE[1:0] BIT-FIELDS AND THE PMDL
MESSAGE TYPE/SIZE
RXLAPDTYPE[1:0]
00
01
10
11
PMDL MESSAGE TYPE
CL Path Identification
Idle Signal Identification
Test Signal Identification
ITU-T Path Identification
PMDL MESSAGE SIZE
76 Bytes
76 Bytes
76 Bytes
82 Bytes
NOTE: Prior to reading in the PMDL Message from the Receive LAPD Message buffer, the user is urged to read the state of
the RxLAPDType[1:0] bit-fields in order to determine the size of this message.
5. Inform the Local Microprocessor/External Circuitry of the receipt of the new LAPD Message frame.
Finally, after the LAPD Receiver has received and processed the newly received LAPD Message frame (per
steps 1 through 4, as described above), it will inform the local Microprocessor that a LAPD Message frame has
been received and is ready for user-system handling. The LAPD Receiver will inform the Microprocessor/
Microcontroller and the external circuitry by:
• Generating a LAPD Message Frame Received interrupt to the Microprocessor. The purpose of this interrupt
is to let the Microprocessor know that the Receive LAPD Message buffer contains a new PMDL Message
that needs to be read and processed. When the LAPD Receiver generates this interrupt, it will set bit 0
(RxLAPD Interrupt Status) within the Rx E3 LAPD Control Register to “1” as depicted below.
RxE3 LAPD Control Register (Address = 0x18)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
DL from NR
BIT 2
RxLAPD
Enable
R/W
R/W
0
0
BIT 1
RxLAPD
Interrupt
Enable
R/W
0
BIT 0
RxLAPD
Interrupt
Status
RUR
1
• Setting Bit 1 (End of Message) within the Rx E3 LAPD Status Register, to “1” as depicted below.
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