XRT72L50 Datasheet, PDF (8/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
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TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ............................................................ 182
Figure 58. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are configured to
be updated on the rising edge of TxLineClk ................................................................................................ 182
4.2.6 Transmit Section Interrupt Processing .................................................................................................. 183
4.2.6.1 Enabling Transmit Section Interrupts .......................................................................................... 183
Figure 59. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are configured to
be updated on the falling edge of TxLineClk ............................................................................................... 183
4.3 THE RECEIVE SECTION OF THE XRT72L50 (DS3 MODE OPERATION) ................................................................. 186
Figure 60. The XRT72L50 Receive Section configured to operate in the DS3 Mode ................................................. 186
4.3.1 The Receive DS3 LIU Interface Block ................................................................................................... 187
4.3.1.1 Unipolar Decoding ....................................................................................................................... 187
Figure 61. The Receive DS3 LIU Interface Block ....................................................................................................... 187
4.3.1.2 Bipolar Decoding ......................................................................................................................... 188
Figure 62. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data ............. 188
TABLE 32: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (UNIPOLAR/BIPOLAR) WITHIN THE I/O CONTROL REGISTER AND
THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ..................................................... 188
Figure 63. IInterfacing the XRT72L50 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU ............................................. 189
Figure 64. AMI Line Code ........................................................................................................................................... 189
Figure 65. Illustration of two examples of B3ZS Decoding ......................................................................................... 190
TABLE 33: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER, AND THE
SAMPLING EDGE OF THE RXLINECLK SIGNAL ................................................................................................... 191
Figure 66. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the rising edge of RxLineClk .................................................................................................... 191
4.3.2 The Receive DS3 Framer Block ............................................................................................................ 192
Figure 67. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the falling edge of RxLineClk ................................................................................................... 192
Figure 68. The Receive DS3 Framer Block and the Associated Paths to Other Functional Blocks ............................ 192
4.3.2.1 Frame Acquisition Mode Operation ............................................................................................. 193
Figure 69. The State Machine Diagram for the Receive DS3 Framer block's Frame Acquisition/Maintenance Algorithm .
193
4.3.2.2 Frame Maintenance Mode Operation ......................................................................................... 194
TABLE 34: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (FRAMING ON PARITY) WITHIN THE RX DS3 CONFIGURATION AND
STATUS REGISTER, AND THE RESULTING FRAMING ACQUISITION CRITERIA ....................................................... 194
TABLE 35: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (F-SYNC ALGO) WITHIN THE RX DS3 CONFIGURATION AND
STATUS REGISTER, AND THE RESULTING F-BIT OOF DECLARATION CRITERIA USED BY THE RECEIVE DS3 FRAMER BLOCK
195
TABLE 36: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 0 (M-SYNC ALGO) WITHIN THE RX DS3 CONFIGURATION AND
STATUS REGISTER, AND THE RESULTING M-BIT OOF DECLARATION CRITERIA USED BY THE RECEIVE DS3 FRAMER
BLOCK ........................................................................................................................................................... 195
4.3.2.3 Forcing a Reframe via Software Command ................................................................................ 196
4.3.2.4 Performance Monitoring of the Receive DS3 Framer block ........................................................ 196
4.3.2.5 DS3 Receive Alarms ................................................................................................................... 197
4.3.2.6 Performance Monitoring of the DS3 Transport Medium .............................................................. 201
Figure 70. A Simple Illustration of the Locations of the Source, Mid-Network and Sink Terminal Equipment (for CP-Bit
Processing) .................................................................................................................................................. 203
4.3.3 The Receive HDLC Controller Block ..................................................................................................... 204
Figure 71. Illustration of the Presumed Configuration of the Mid-Network Terminal Equipment ................................. 204
4.3.3.1 Bit-Oriented Signaling (or FEAC) Processing via the Receive DS3 HDLC Controller. ............... 205
4.3.3.2 The Message Oriented Signaling (e.g., LAP-D) Processing via the Receive DS3 HDLC Controller block
207
Figure 72. Flow Diagram depicting how the Receive FEAC Processor Functions ...................................................... 207
Figure 73. LAPD Message Frame Format .................................................................................................................. 208
TABLE 37: THE RELATIONSHIP BETWEEN RXLAPDTYPE[1:0] AND THE RESULTING LAPD MESSAGE TYPE AND SIZE .......... 209
4.3.4 The Receive Overhead Data Output Interface ...................................................................................... 211
Figure 74. Flow Chart depicting the Functionality of the LAPD Receiver ................................................................... 211
4.3.4.1 Method 1 - Using the RxOHClk Clock signal ............................................................................... 212
Figure 75. The Receive Overhead Output Interface block .......................................................................................... 212
TABLE 38: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
213
Figure 76. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface Block (Method 1)
213
TABLE 39: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXOHFRAME WAS LAST
SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN ................. 214
Figure 77. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method 1). ....... 216
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