XRT72L50 Datasheet, PDF (336/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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Each of the output pins of the Receive Payload Data Output Interface block are listed in Table 64 and described
below. The exact role that each of these output pins assume, for a variety of operating scenarios are described
throughout this section.
TABLE 64: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT
INTERFACE BLOCK
SIGNAL NAME TYPE
DESCRIPTION
RxSer
Output
Receive Serial Payload Data Output pin:
If the user opts to operate the XRT72L50 in the serial mode, then the chip will output the pay-
load data, of the incoming E3 frames, via this pin. The XRT72L50 will output this data upon
the rising edge of RxClk.
The user is advised to design the Terminal Equipment such that it will sample this data on the
falling edge of RxClk.
This signal is only active if the NibIntf input pin is pulled "Low".
RxNib[3:0]
Output
Receive Nibble-Parallel Payload Data Output pins:
If the user opts to operate the XRT72L50 in the nibble-parallel mode, then the chip will output
the payload data, of the incoming E3 frames, via these pins. The XRT72L50 will output data
via these pins, upon the falling edge of the RxClk output pin.
The user is advised to design the Terminal Equipment such that it will sample this data upon
the rising edge of RxClk.
NOTE: These pins are only active if the NibIntf input pin is pulled "High".
RxClk
Output
Receive Payload Data Output Clock pin:
The exact behavior of this signal depends upon whether the XRT72L50 is operating in the
Serial or in the Nibble-Parallel-Mode.
Serial Mode Operation
In the serial mode, this signal is a 34.368MHz clock output signal. The Receive Payload Data
Output Interface will update the data via the RxSer output pin, upon the rising edge of this
clock signal.
The user is advised to design (or configure) the Terminal Equipment to sample the data on the
RxSer pin, upon the falling edge of this clock signal.
Nibble-Parallel Mode Operation
In this Nibble-Parallel Mode, the XRT72L50 will derive this clock signal, from the RxLineClk
signal. The XRT72L50 will pulse this clock 1060 times for each inbound E3 frame. The
Receive Payload Data Output Interface will update the data, on the RxNib[3:0] output pins
upon the falling edge of this clock signal.
The user is advised to design (or configure) the Terminal Equipment to sample the data on the
RxNib[3:0] output pins, upon the rising edge of this clock signal
RxOHInd
Output
Receive Overhead Bit Indicator Output:
This output pin will pulse "High" whenever the Receive Payload Data Output Interface outputs
an overhead bit via the RxSer output pin. The purpose of this output pin is to alert the Termi-
nal Equipment that the current bit, (which is now residing on the RxSer output pin), is an over-
head bit and should not be processed by the Terminal Equipment.
The XRT72L50 will update this signal, upon the rising edge of RxOHInd.
The user is advised to design (or configure) the Terminal Equipment to sample this signal
(along with the data on the RxSer output pin) on the falling edge of the RxClk signal.
RxFrame
Output
Receive Start of Frame Output Indicator:
The exact behavior of this pin, depends upon whether the XRT72L50 has been configured to
operate in the Serial Mode or the Nibble-Parallel Mode.
Serial Mode Operation:
The Receive Section of the XRT72L50 will pulse this output pin "High" (for one bit period)
when the Receive Payload Data Output Interface block is driving the very first bit (or Nibble) of
a given E3 frame, onto the RxSer output pin.
Nibble-Parallel Mode Operation:
The Receive Section of the XRT72L50 will pulse this output pin "High" for one nibble period,
when the Receive Payload Data Output Interface is driving the very first nibble of a given E3
frame, onto the RxNib[3:0] output pins.
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