XRT72L50 Datasheet, PDF (310/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FIGURE 124. THE STATE MACHINE DIAGRAM FOR THE RECEIVE E3 FRAMER E3 FRAME ACQUISITION/MAINTENANCE
ALGORITHM
FAS
Pattern
Search
FAS pattern is
detected once
FAS
Pattern
Verification
FAS Pattern is
not detected
LOF
Condition
FAS Pattern is
verified once
8 or 24 framing periods
of operating in the
OOF condition
(user-selectable)
OOF
Condition
3 consecutive
Valid Frames
4 consecutive
In-valid Frames
In Frame
Frame Maintenance
Mode
FIGURE 125. ILLUSTRATION OF THE E3, ITU-T G.751 FRAMING FORMAT
1
10 11 12
Frame
Alignment
Signal
AN
384 385
768 769
1152 1153
1532
1536
Data
Data
Data
Data
BIP-4
if Selected
Framing Alignment Signal Pattern = 1111010000
When the Receive E3 Framer block detects the FAS pattern, it will then transition over to the FAS Pattern
Verification state, per Figure 125.
297