XRT72L50 Datasheet, PDF (220/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
áç
FIGURE 72. FLOW DIAGRAM DEPICTING HOW THE RECEIVE FEAC PROCESSOR FUNCTIONS
SSTTAARRTT
11
EENNAABBLLEETTHHEE““FFEEAACCRREEMMOOVVAALLAANNDD
““VVAALLIDIDAATTIOIONN””ININTTEERRRRUUPPTTSS. _.
TThhisisisisacaccocmomplpilsihshededbbyywwrirtiitningg“x“xxxxxxx10110010””inintotoththee
“R“RxxDDSS33FFEEAACCInItnetrerruruppt/tS/Stattautus _{sRRegegisitsetrer(A(Addddrersesss==00xx1177) )}
RREECCEEIVIVEEFFEEAACCPPRROOCCEESSSSOORRBBEEGGININSSRREEAADDININGGININ
TTHHEEFFEEAACCBBITIT-F-FIEIELLDDSS(O(OFFININCCOOMMININGGDDSS33FFRRAAMMEESS) ₎
TTheheRReceecievieveFFEEAACCPProrcoecsessosrorchcehcekcsksfofrorthtehe“F“FEEAACCFFrarmaminigng
AAlilgignnmmenent”t”ppatattetrenrnoof _{f“0“011111111111100”.”.}
HHasasththisis
sasmameeFFEEAACC
CCooddeeWWoordrdbbeeenen
YES
RReceecievivededinin88oouut _{toof fththeelalsatst}
1100FFEEAACCMMesessasgagee
RReceecpeptitoionns?s?
NO
GGEENNEERRAATTEE““FFEEAACC
VVAALLIDIDAATTIOIONN””ININTTEERRRRUUPPTT
ININVVOOKKEE“F“FEEAACCVVAALLIDIDAATTIOIONN””
ININTTEERRRRUUPPTTSSEERRVVICICEERROOUUTTININEE. _.
IsIsththee
“F“FEEAACCFFrarmaminingg
AAlilgignnmmenent”tp”patattetrenrn
NO
pprerseesnent _{tininththeeFFEEAACC NO}
CChhanannenlel
??
YES
RREEAADDININTTHHEE““66-B-BITITFFEEAACCCCOODDEEWWOORRDD””
TThehe6-6b-ibtitFFEEAACCCCodoedeWWorodrdimimmmedeidaitaetleylyfoflollolwows _{sthtehe“F“FEEAACC}
FFrarmamininggAAlilgingmnmenetn”t”PPatattetrenr.n.
HHasasa _aFFEEAACC
CCooddeeWWoordrd(o(oththererththanan
ththeelalsatst“V“ValaildidataetdedCCodoedeWWorodr)d)
bbeeenenRReceecievivededinin33oouut _{toof fththeelalsatst}
1100FFEEAACCMMesessasgagee
RReceecpetpitoinosn?s?
11
YES
GGEENNEERRAATTEE““FFEEAACC
RREEMMOOVVAALL””ININTTEERRRRUUPPTT
11
ININVVOOKKEE““FFEEAACCRREEMMOOVVAALL””
ININTTEERRRRUUPPTTSSEERRVVICICEERROOUUTTININEE. _.
NOTES:
1. The white (e.g., unshaded) boxes reflect tasks that the user’s system must perform in order to configure the
Receive FEAC Processor to receive FEAC messages.
2. A brief description of the steps that must exist within the FEAC Validation and FEAC Removal Interrupt Service
Routines exists in Section 4.3.3
4.3.3.2 The Message Oriented Signaling (e.g., LAP-D) Processing via the Receive DS3 HDLC
Controller block
The LAPD Receiver (within the Receive DS3 HDLC Controller block) allows the user to receive PMDL
messages from the remote terminal equipment, via the inbound DS3 frames. In this case, the inbound
message bits will be carried by the 3 DL bit-fields of F-Frame 5, within each DS3 M-Frame. The remote LAPD
Transmitter will transmit a LAPD Message to the Near-End Receiver via these three bits within each DS3
Frame. The LAPD Receiver will receive and store the information portion of the received LAPD frame into the
Receive LAPD Message Buffer, which is located at addresses: 0xDE through 0x135 within the on-chip RAM.
The LAPD Receiver has the following responsibilities.
• Framing to the incoming LAPD Messages
• Filtering out stuffed “Zeros” (Between the two flag sequence bytes, 0x7E)
• Storing the Frame Message into the Receive LAPD Message Buffer
• Perform Frame Check Sequence (FCS) Verification
• Provide status indicators for
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