XRT72L50 Datasheet, PDF (464/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
Local Loop-back
BIT 6
DS3/E3
R/W
R/W
1
X
BIT 5
Internal
LOS
Enable
R/W
X
BIT 4
RESET
BIT 3
Interrupt
Enable Reset
BIT 2
Frame Format
R/W
R/W
R/W
0
X
X
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
X
X
When the XRT72L50 DS3/E3 Framer IC is operating in the Framer Local-Loop-back Mode, no data will be
output via the TxPOS and TxNEG output pins.
The XRT72L50 cannot be configured to operate in the Framer Local Loop-back Mode if it is configured to
operate in Mode 1 or Mode 4 (Loop-Timing Modes). The XRT72L50 Framer must be configured to operate in
one of the Local-Timing modes.
8.0 HIGH SPEED HDLC CONTROLLER MODE OF OPERATION
The XRT72L50 can be configured to operate in the High-Speed HDLC Controller Mode. Whenever it is
configured to operate in this mode then the following happens:
1. The Transmit Section of the XRT72L50 will be configured to accept outbound data from the user’s Terminal
Equipment via an 8-bit wide input interface labeled TxHDLCDat[7:0]. The Transmit Section then encapsu-
lates all data that it receives via TxHDLCDat[7:0].
2. The Transmit Section of the XRT72L50 then encapsulates all data that it receives via the TxHDLCDat[7:0]
interface into HDLC frames. These HDLC frames are variable-length packets transported to the remote
terminal equipment via the outbound DS3 or E3 payload data bits.
3. As the Transmit Section accepts and processes data from the user’s terminal equipment, it performs all the
necessary “0” stuffing into the outbound HDLC frame in order to prevent the user-supplied data from mim-
icking either the flag sequence octet (0x7E) or the ABORT sequence.
4. The Transmit Section can also be configured to compute and append either a 16-bit or 32-bit CRC value to
the end of this “0” stuffed user’s data as a trailer.
5. Whenever the Transmit Section has no user data to send to the remote terminal equipment via HDLC
frames, then it transmits a continuous stream of flag sequence octets (0x7E) via the DS3 or E3 payload
bits.
6. The Receive Section of the XRT72L50 will be configured to receive and extract out these HDLC frames via
the inbound DS3/E3 data stream. The Receive Section then outputs the contents of these received HDLC
frames in a byte-wide manner via the RxHDLCDat[7:0] output pins.
7. If the Receive Section of the XRT72L50 is only receiving a stream of flag sequences (0x7E), then it will ter-
minate this data stream and will not output any data via the RxHDLCDat[7:0] output pins.
8. As the Receive Section of the XRT72L50 receives these HDLC frames, it does the following.
• Compute and verify the 16-bit or 32-bit CRC value which has been appended to the HDLC frame, as a trailer.
• Perform the necessary “0” un-stuffing in order to restore the original content of the user-supplied data.
8.1 Configuring the XRT72L50 to operate in the High Speed HDLC Controller Mode
The XRT72L50 can be configured to operate in the High-Speed HDLC Controller Mode bit 6 (HDLC ON) within
HDLC Control register address location 0x82, to “1”, as depicted below.
NOTE: The NibIntf pin (25), must also be set “High” for HDLC mode of operation.
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