XRT72L50 Datasheet, PDF (251/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
To enable or disable the Receive LAPD Message Interrupt, write the appropriate data into Bit 1 (RxLAPD
Interrupt Enable) within the RxDS3 LAPD Control Register, as indicated below.
RxDS3 LAPD Control Register (Address = 0x18)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
RxLAPD
Enable
RxLAPD
Interrupt
Enable
RxLAPD
Interrupt
Status
RO
RO
RO
RO
RO
R/W
R/W
RUR
0
0
0
0
0
0
X
0
Writing a “1” into this bit-field enables the Receive LAPD Message Interrupt. Conversely, writing a “0” into this
bit-field disables the Receive LAPD Message interrupt.
Servicing the Receive LAPD Message Interrupt
Whenever the XRT72L50 Framer IC generates this interrupt, it will do the following.
• It will assert the Interrupt Request output pin (Int) by driving it "Low".
• It will set Bit 0 (RxLAPD Interrupt Status), within the Rx DS3 LAPD Control Register to “1”, as indicated
below.
RxDS3 LAPD Control Register (Address = 0x18)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
RxLAPD
Enable
RxLAPD
Interrupt
Enable
RxLAPD
Interrupt
Status
RO
RO
RO
RO
RO
R/W
R/W
RUR
0
0
0
0
0
0
1
1
• It will write the contents of this newly Received LAPD Message into the Receive LAPD Message buffer
(located at 0xDE through 0x135).
Whenever the Terminal Equipment encounters the Receive LAPD Interrupt, then it should read out the
contents of the Receive LAPD Message buffer, and respond accordingly.
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