XRT72L50 Datasheet, PDF (5/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
2.3.5.5 Transmit DS3 LAPD Status and Interrupt Register ....................................................................... 87
2.3.5.6 Transmit DS3 M-Bit Mask Register ............................................................................................... 88
2.3.5.7 Transmit DS3 F-Bit Mask Register 1 ............................................................................................. 89
2.3.5.8 Transmit DS3 F-Bit Mask Register 2 ............................................................................................. 89
2.3.5.9 Transmit F-Bit Mask Register 3 ..................................................................................................... 89
2.3.5.10 Transmit F-Bit Mask Register 4 ................................................................................................... 90
2.3.6 Transmit E3 (ITU-T G.832) Configuration Registers ............................................................................... 90
2.3.6.1 Transmit E3 Configuration Register (E3, ITU-T G.832) ................................................................ 90
2.3.6.2 Transmit E3 LAPD Configuration Register (E3, ITU-T G.832) ...................................................... 91
2.3.6.3 Transmit E3 LAPD Status and Interrupt Register (E3, ITU-T G.832) ............................................ 92
2.3.6.4 Transmit E3 GC Byte Register (E3, ITU-T G.832) ........................................................................ 93
2.3.6.5 Transmit E3 MA Byte Register (E3, ITU-T G.832) ........................................................................ 93
2.3.6.6 Transmit E3 NR Byte Register (E3, ITU-T G.832) ........................................................................ 94
2.3.6.7 Transmit E3 TTB-0 Register (E3, ITU-T G.832) ............................................................................ 94
2.3.6.8 Transmit E3 TTB-1 Register (E3, ITU-T G.832) ............................................................................ 95
2.3.6.9 Transmit E3 TTB-2 Register (E3, ITU-T G.832) ............................................................................ 95
2.3.6.10 Transmit E3 TTB-3 Register (E3, ITU-T G.832) .......................................................................... 96
2.3.6.11 Transmit E3 TTB-4 Register (E3, ITU-T G.832) .......................................................................... 96
2.3.6.12 Transmit E3 TTB-5 Register (E3, ITU-T G.832) .......................................................................... 96
2.3.6.13 Transmit E3 TTB-6 Register (E3, ITU-T G.832) .......................................................................... 97
2.3.6.14 Transmit E3 TTB-7 Register (E3, ITU-T G.832) .......................................................................... 97
2.3.6.15 Transmit E3 TTB-8 Register (E3, ITU-T G.832) .......................................................................... 98
2.3.6.16 Transmit E3 TTB-9 Register (E3, ITU-T G.832) .......................................................................... 98
2.3.6.17 Transmit E3 TTB-10 Register (E3, ITU-T G.832) ........................................................................ 98
2.3.6.18 Transmit E3 TTB-11 Register (E3, ITU-T G.832) ........................................................................ 99
2.3.6.19 Transmit E3 TTB-12 Register (E3, ITU-T G.832) ........................................................................ 99
2.3.6.20 Transmit E3 TTB-13 Register (E3, ITU-T G.832) ...................................................................... 100
2.3.6.21 Transmit E3 TTB-14 Register (E3, ITU-T G.832) ...................................................................... 100
2.3.6.22 Transmit E3 TTB-15 Register (E3, ITU-T G.832) ...................................................................... 100
2.3.6.23 Transmit E3 FA1 Byte Error Mask Register (E3, ITU-T G.832) ................................................ 101
2.3.6.24 Transmit E3 FA2 Byte Error Mask Register (E3, ITU-T G.832) ................................................ 101
2.3.6.25 Transmit E3 BIP-8 Error Mask Register (E3, ITU-T G.832) ...................................................... 101
2.3.6.26 TxE3 SSM Register - G.832 ..................................................................................................... 102
2.3.7 Transmit E3 Framer Configuration Registers (ITU-T G.751) ................................................................ 102
2.3.7.1 Transmit E3 Configuration Register (ITU-T G.751) ..................................................................... 102
2.3.7.2 Transmit E3 LAPD Configuration Register (ITU-T G.751) .......................................................... 104
2.3.7.3 Transmit E3 LAPD Status and Interrupt Register (ITU-T G.751) ................................................ 104
2.3.7.4 Transmit E3 Service Bits Register (ITU-T G.751) ....................................................................... 105
2.3.7.5 Transmit E3 FAS Mask Register - 0 (ITU-T G.751) .................................................................... 106
2.3.7.6 Transmit E3 FAS Error Mask Register - 1 (ITU-T G.751) ........................................................... 106
2.3.7.7 Transmit E3 BIP-4 Error Mask Register (ITU-T G.751) .............................................................. 106
2.3.8 Performance Monitor Registers ............................................................................................................. 107
2.3.8.1 PMON Line Code Violation Count Register - MSB ..................................................................... 107
2.3.8.2 PMON Line Code Violation Count Register - LSB ...................................................................... 107
2.3.8.3 PMON Framing Bit/Byte Error Count Register - MSB ................................................................. 107
2.3.8.4 PMON Framing Bit/Byte Error Count Register - LSB .................................................................. 108
2.3.8.5 PMON Parity Error Count Register - MSB .................................................................................. 108
2.3.8.6 PMON Parity Error Count Register - LSB ................................................................................... 108
2.3.8.7 PMON FEBE Event Count Register - MSB ................................................................................. 109
2.3.8.8 PMON FEBE Event Count Register - LSB .................................................................................. 109
2.3.8.9 PMON CP-Bit Error Event Count Register - MSB ....................................................................... 109
2.3.8.10 PMON CP-Bit Error Event Count Register - LSB ...................................................................... 110
2.3.8.11 PRBS Error Count Register - MSB ........................................................................................... 110
2.3.8.12 PRBS Error Count Register - LSB ............................................................................................ 110
2.3.8.13 PMON Holding Register ........................................................................................................... 111
2.3.8.14 One-Second Error Status Register ........................................................................................... 111
2.3.8.15 One-Second Line Code Violation Accumulator Register - MSB ............................................... 111
2.3.8.16 One-Second Line Code Violation Accumulator Register - LSB ................................................ 112
2.3.8.17 One-Second Frame Parity Error Accumulator Register - MSB ................................................. 112
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