XRT72L50 Datasheet, PDF (135/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE 9: INTERRUPT SERVICE ROUTINE GUIDE (FOR DS3 APPLICATIONS)
INTERRUPTING
FUNCTIONAL BLOCK
THE NEXT REGISTERS TO BE READ DURING THE INTERRUPT SERVICE
ROUTINE
REGISTER ADDRESS
Receive Section RxDS3 Interrupt Status Register
0 x 13
RxDS3 FEAC Interrupt Enable/Status Register
0 x 17
RxDS3 LAPD Control Register
0 x 18
Transmit Section TxDS3 FEAC Configuration and Status Register
0 x 31
TxDS3 LAPD Status/Interrupt Register
0 x 34
TABLE 10: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.832 APPLICATIONS)
INTERRUPTING
FUNCTIONAL BLOCK
THE NEXT REGISTERS TO BE READ DURING THE INTERRUPT SERVICE
ROUTINE
REGISTER ADDRESS
Receive Section RxE3 Interrupt Status Register - 1
0 x 14
RxE3 Interrupt Status Register - 2
0 x 15
RxE3 LAPD Control Register
0 x 18
Transmit Section TxE3 LAPD Status and Interrupt Register
0 x 34
TABLE 11: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.751 APPLICATIONS)
INTERRUPTING
FUNCTIONAL BLOCK
THE NEXT REGISTERS TO BE READ DURING THE INTERRUPT SERVICE
ROUTINE
Receive Section RxE3 Interrupt Status Register - 1
RxE3 Interrupt Status Register - 2
RxE3 LAPD Control Register
Transmit Section TxE3 LAPD Status and Interrupt Register
REGISTER ADDRESS
0 x 014
0 x 15
0 x 18
0 x 34
Once the Microprocessor/Microcontroller has read the register that corresponds to the interrupting source, the
following happens:
1. The Asserted Interrupt Status bit-fields within this register will be reset upon read.
2. The Asserted bit-field, within the Block Interrupt Status register will be reset.
3. The Framer will negate the Int (Interrupt Request) output pin, by drving this output pin "High”.
2.6.1 Automatic Reset of Interrupt Enable Bits
Occassionally, the user’s system (which includes the Framer) may experience a fault condition, such that a
Framer Interrupt Condition will continuously exist. If this particular interrupt condition has been enabled, then
the Framer will generate an interrupt request to the MIcroprocessor/Microcontroller. Afterwards, the
Microprocessor/Microcontroller will attempt to service this interrupt by reading the Block Interrupt Status
register and the subsequent source level interrupt status registers. Additionally, the Microprocessor/
Microcontroller will attempl to perform some system-related tasks in order to try to resolve those conditions
causing the interrupt. After the Microprocessor/Microcontroller has attempted all of these things, the Framer IC
will negate the Int output pin. However, because the system fault still remains, the conditions causing the
Framer to issue this interrupt request, also still exists. Consequently, the Framer will generate another interrupt
request, which forces the Microprocessor/Microcontroller to once again attempt to service this interrupt. This
phenomenon quickly results in the local Microprocessor/Microcontroller being tied up in a continuous cycle of
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