XRT72L50 Datasheet, PDF (51/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
(located at Address = 0x51). These two eight-bit registers, when concatenated together, make up the PMON
LCV Event Count Register.
If the 8-bit µC/µP reads in the PMON LCV Event Count-LSB register first, then the entire PMON LCV Event
Count register will be reset to 0x0000. And if the 8-bit µC/µP attempts to read in the PMON LCV Event Count-
MSB register in the very next read cycle, it will read in the value 0x00.
PMON Holding Register
To resolve this Reset-Upon-Read problem, the XRT72L50 DS3/E3 Framer includes a special register which
permits an 8-bit µC/µP to read in the full 16-bit contents of these PMON registers. This register is called the
PMON Holding Register and is located at 0x6c within the Framer Address space.
Whenever an 8-bit µC/µP reads in one of the bytes of the 2-byte PMON register, the contents of the unread
byte will be stored in the PMON Holding Register. The 8-bit µC/µP must then read in the contents of the
PMON Holding Register in the very next read operation.
Whenever an 8-bit µC/µP needs to read a PMON Register, it must execute the following steps.
Step 1: Read in the contents of a given 8-bit PMON Register. It does not matter whether the µC/µP reads in
the MSB or the LSB register.
Step 2: Read in the contents of the PMON Holding Register (located at Address = 0x6c). This register will
contain the contents of the other byte.
2.2.2 Data Access Modes
The Microprocessor Interface block supports data transfer between the Framer and the µC/µP (e.g., Read and
Write operations) via two modes: the Programmed I/O and the Burst Modes.
2.2.2.1 Data Access using Programmed I/O
Programmed I/O is the conventional manner in which a microprocessor exchanges data with a peripheral
device. It is also the slowest method of data exchange between the Framer and the µC/µP.
2.2.2.1.1
Programmed I/O Access in the Intel Mode
If the XRT72L50 DS3/E3 Framer is interfaced to an Intel-type µC/µP, then it should be configured to operate in
the Intel mode by tying the MOTO pin to ground.
The Intel Mode Read Cycle
Whenever an Intel-type µC/µP wishes to read the contents of a register or some location within the Receive
LAPD Message buffer, it should do the following.
1. Place the address of the target register or buffer location on the Address Bus input pins A[8:0].
2. While the µC/µP is placing this address value on the Address Bus, the Address Decoding circuitry (within
the user's system) should assert the CS (Chip Select) pin of the Framer, by toggling it "Low". This action
enables further communication between the µC/µP and the Framer Microprocessor Interface block.
3. Toggle the ALE_AS (Address Latch Enable) input pin "High". This step enables the Address Bus input
drivers, within the Microprocessor Interface block of the Framer.
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate Address Data Setup
time), the µC/µP should toggle the ALE_AS pin "Low". This step causes the Framer to latch the contents
of the Address Bus into its internal circuitry. At this point, the address of the register or buffer locations has
now been selected.
5. Next, the µC/µP should indicate that this current bus cycle is a Read Operation by toggling the RD_DS
(Read Strobe) input pin "Low". This action also enables the bi-directional data bus output drivers of the
Framer. At this point, the bi-directional data bus output drivers will proceed to drive the contents of the
latched addressed register or buffer location onto the bi-directional data bus, D[7:0].
6. After the µC/µP toggles the Read Strobe signal "Low", the Framer will keep the RDY_DTCK output pin
"High" in order to inform the µC/µP that the data to be read from the data bus is NOT READY to be latched
into the µC/µP.
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