XRT72L50 Datasheet, PDF (80/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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NOTE: Please see Section 6.3.6.2.6 for a more detailed discussion of this interrupt.
Bit 4 - FEBE (Far-End Block Error) Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the FEBE (Far-End-Block Error) interrupt has occurred since
the last read of this register.
The Receive DS3/E3 Framer block will generate the FEBE interrupt anytime it detects a "1" in the FEBE bit-
field within an incoming E3 frame.
NOTE: Please see Section 6.3.6.2.8 for a more detailed discussion of this interrupt.
Bit 3 - FERF Interrupt Status
This Reset Upon Read bit will be set to '1' if the Receive E3 Framer has detected a Change in the Rx FERF
Condition, since the last time this register was read.
This bit-field will be asserted under either of the following two conditions.
1. When the Receive DS3/E3 Framer block first detects the occurrence of an RxFERF Condition (e.g., when
the FERF bit, within the last 3 or 5 consecutive E3 frames are set to "1").
2. When the Receive DS3/E3 Framer block detects the end of the RxFERF Condition (e.g., when the FERF
bit, within the last 3 or 5 consecutive E3 frames are set to "0").
NOTE: For more information on the RxFERF (Yellow Alarm) condition, refer to Section 6.3.2.6.3.
Bit 2 - BIP-8 (EM Byte) Error Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the BIP-8 Error interrupt has occurred since the last read of
this register.
The Receive DS3/E3 Framer block will generate the BIP-8 Error interrupt if it has concluded that it has received
an errored E3 frame, from the Remote Terminal.
NOTE: Please see Section 6.3.6.2.9 for a more detailed discussion of this interrupt.
Bit 1 - Framing Byte Error Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the Framing Byte Error interrupt has occurred since the last
read of this register.
The Receive DS3/E3 Framer block will generate the Framing Byte Error interrupt if it has detected an error in
the FA1 or FA2 bytes, on an incoming E3 frame.
NOTE: Please see Section 6.3.6.2.10 for a more detailed discussion of this interrupt.
Bit 0 - Rx Pld Mis Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the Payload Type Mismatch interrupt has occurred since the
last read of this register.
The Receive DS3/E3 Framer block will generate the Payload Type Mismatch interrupt when it detects that the
values, within the Payload Type bit-fields of the incoming E3 frame, has changed from that of the previous E3
frame.
NOTE: Please see Section 6.3.6.2.11 for a more detailed discussion on this interrupt.
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