XRT72L50 Datasheet, PDF (133/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE 7: A LISTING OF THE XRT72L50 FRAMER INTERRUPT BLOCK REGISTERS (FOR E3, ITU-T G.832
APPLICATIONS)
ADDRESS LOCATION
REGISTER NAME
0 x 04
Block Interrupt Enable Register
0 x 05
Block Interrupt Status Register
0 x 12
RxE3 Interrupt Enable Register -1
0 x 13
RxE3 Interrupt Enable Register -2
0 x 14
RxE3 Interrupt Status Register - 1
0 x 15
RxE3 Interrupt Status Register - 2
0 x 18
RxE3 LAPD Control Register
0 x 34
TxE3 LAPD Status/Interrupt Status
TABLE 8: A LISTING OF THE XRT72L50 FRAMER INTERRUPT BLOCK REGISTER (FOR E3, ITU-T G.751
APPLICATIONS)
ADDRESS LOCATION
0 x 04
Block Interrupt Enable Register
0 x 05
Block Interrupt Status Register
0 x 12
RxE3 Interrupt Enable Register -1
0 x 13
RxE3 Interrupt Enable Register -2
0 x 14
RxE3 Interrupt Status Register - 1
0 x 15
RxE3 Interrupt Status Register - 2
0 x 18
RxE3 LAPD Control Register
0 x 34
TxE3 LAPD Status/Interrupt Status
REGISTER NAME
General Flow of Framer Chip Interrupt Servicing
When any of the conditions, presented in Table 5 occurs, (if their Interrupts is enabled), then the Framer will
generate an interrupt request to the local µP/µC by asserting the active-low interrupt request output pin, Int.
Shortly after the local µP/µC has detected the activated Int signal, it will enter into the appropriate user-
supplied interrupt service routine. The first task for the local µP/µC, while running this interrupt service routine,
may be to isolate the source of the interrupt request down to the device level (e.g., the XRT72L50 Framer), if
multiple peripheral devices exist in the user's system. However, once the interrupting peripheral device has
been identified, the next task for the local µP/µC is to determine exactly what feature or functional section
within the device requested the interrupt.
Determine the Channel and Functional Block(s) Requesting the Interrupt
If the interrupt device turns out to be the XRT72L50 DS3/E3 Framer IC, then the local µC/µP must determine
which channel functional block requested the interrupt. Hence, upon reaching this state, one of the very first
things that the local µC/µP must do within the user supplied Framer Interrupt Service routine, is to perform a
read of the Block Interrupt Status Register (Address = 0x05) for every channel within the XRT72L50 Framer.
The bit format of the Block Interrupt Status register is presented below.
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