XRT72L50 Datasheet, PDF (64/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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NOTE: Setting this bit-field to "1" does not enable all Transmit Section related Interrupts. Each of these interrupts can still
be disabled at the Source Level. However, setting this bit-field to "0" does disable all Transmit Section related
Interrupts.
Bit 0 - One-Second Interrupt Enable
This Read/Write bit-field permits the user to enable or disable the One-Second Interrupt. If this interrupt is
enabled, then the XRT72L50 generate interrupts to the µC/µP at one-second intervals.
Setting this bit-field to "0" disables the One-Second Interrupt. Conversely, setting this bit-field to "1" enables
the One-Second Interrupt.
2.3.2.6 Block Interrupt Status Register
Block Interrupt Status Register (Address = 0x05)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxDS3/E3
Interrupt
Status
Not Used
TxDS3/E3
Interrupt
Status
One-Second
Interrupt
Status
RO
RO
RO
RO
RO
RO
RO
RUR
0
0
0
0
0
0
0
1
Bit 7 - RxDS3/E3 Interrupt Status Indicator
This Read-Only bit-field indicates whether or not a Receive-Section related interrupt has been requested and
is awaiting service.
If this bit-field is set to "0", then there are no Receive-Section related interrupts awaiting service. Conversely, if
this bit-field is set to "1", then there is at least one Receive Section related interrupt, awaiting service.
If this bit-field is set to "1", then the µC/µP must read the Source-Level Interrupt Status register in order to clear
this bit-field.
Bit 1 - TxDS3/E3 Interrupt Status Indicator
This Read-Only bit-field indicates whether or not a Transmit-Section related interrupt has been requested and
is awaiting service.
If this bit-field is set to "0", then there are no Transmit-Section related interrupts awaiting service. Conversely, if
this bit-field is set to "1", then there is at least one Transmit Section related interrupt, awaiting service.
If this bit-field is set to "1", then the µC/µP must read the Source-Level Interrupt Status register in order to clear
this bit-field.
Bit 0 - One-Second Interrupt Status
This Reset-upon-Read bit field indicates whether or not a One-Second interrupt has been requested and is
awaiting service.
If this bit-field is set to "0", then the One-Second interrupt is not awaiting service. Conversely, if this bit-field is
set to "1", then the One-Second interrupt is awaiting service.
This bit-field will be cleared immediately after the µC/µP has read this register.
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