XRT72L50 Datasheet, PDF (101/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
2.3.5.6 Transmit DS3 M-Bit Mask Register
TxDS3 M-Bit Mask Register (Address = 0x35)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxFEBEDat[2:0]
FEBE Reg
Enable
Tx Error
P-Bit
MBit Mask[2] MBit Mask[1] MBit Mask[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 - 5: TxFEBEDat[2:0]
These three (3) read/write bit-fields, along with Bit 4 of this register, allows the user to configure and transmit
his/her choice for the three (3) FEBE (Far-End Block Error) bits in each outgoing DS3 Frame. The user will
write his/her value for the FEBE bits into these bit-fields. The Transmit DS3 Framer block will insert these
values into the FEBE bit-fields of each outgoing DS3 Frame, once the user has written a "1" to Bit 4 (FEBE
Register Enable).
NOTE: For more information on this feature, refer to Section 4.2.4.2.1.9.
Bit 4 - FEBE Register Enable
This Read/Write bit-field permits the user to configure the Transmit DS3 Framer to insert the contents of
TxFEBEDat[2:0] into the FEBE bit-fields each outbound DS3 Frame.
Writing a "0" to this bit-field disables this feature (e.g., the Transmit DS3 Framer block will transmit the internally
generated FEBE bits). Writing a "1" to this bit-field enables this features (e.g., the internally generated FEBE
bits are overwritten by the contents of the TxFEBEDat[2:0] bit-field).
NOTE: For more information on this feature, refer to Section 4.2.4.2.1.9.
Bit 3 - Transmit Erred P-Bit
This Read/Write bit-field permits the user to insert errors into the P-bits within the outbound DS3 frames (via
the Transmit DS3/E3 Framer block). If the user enables this feature, then the Transmit DS3/E3 Framer block
will proceed to invert each and every P-bit, from its computed value, prior to transmission to the Remote
Terminal.
Writing a "0" to this bit-field (the default condition) disables this feature (e.g., the correct P-bits are sent).
Writing a "1" to this bit-field enables this feature (e.g., the incorrect P-bits are sent).
NOTE: For more information on this feature, refer to Section 4.2.4.2.2.
Bit 2 - 0 M-Bit Mask[2:0]
These Read/Write bit-fields permit the user to insert errors in the M-bits for Test and Diagnostic purposes. The
Transmit DS3/E3 Framer block automatically performs an XOR operation on the actual contents of the M-bit
fields to these register bit-fields. Therefore, for every '1' that exists in these bit-fields, will result in a change of
state of the corresponding M-bit, prior to being transmitted to the Remote Terminal Equipment.
If the Transmit DS3/E3 Framer block is to be operated in the normal mode (e.g., when no errors are being
injected into the M-bit fields of the outbound DS3 Frame), then these bit-fields must be all “0’s”.
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