XRT72L50 Datasheet, PDF (107/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
NOTE: The values written into bit-fields 6 (FEBE) and 7 (FERF) are inserted into outbound E3 frames, only if bit-field 0
(TxMARx) within the Tx E3 Configuration Register (Address = 0x30) is set to "0". Otherwise, the Transmit DS3/E3
Framer block will set the FERF and FEBE values, within each outbound E3 frame, to values based upon Receive
DS3/E3 Framer block conditions.
2.3.6.5.2
The October 1998 Revision
If the channel has been configured to support the October 1998 revision of the ITU-T G.832 framing format for
E3; then the bit-format of the TxE3 MA Byte register is as presented below.
TxE3 MA Byte Register (Address = 0x36)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit MA Byte
FERF
FEBE
Payload Type
MFI[1:0]
SSM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
0
0
0
This Read/Write byte-fields permits the user to specify the contents of the MA byte-field in each outbound E3
frame.
NOTE: The values written into bit-fields 6 (FEBE) and 7 (FERF) are inserted into outbound E3 frames, only if bit-field 0
(TxMARx) within the Tx E3 Configuration Register (Address = 0x30) is set to "0". Otherwise, the Transmit DS3/E3
Framer block will set the FERF and FEBE values, within each outbound E3 frame, to values based upon Receive
DS3/E3 Framer block conditions.
2.3.6.6 Transmit E3 NR Byte Register (E3, ITU-T G.832)
TxE3 NR Byte Register (Address = 0x37)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxNR[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
This Read/Write byte-field permits the user to specify the contents of the NR byte-field in each outbound E3
frame.
NOTE: The contents of this register is ignored, if the LAPD Transmitter is enabled and has been configured to insert the
comprising octets of an outbound LAPD Message frame into the NR byte-field of each outbound E3 frame (e.g., if
DLinNR = "1").
2.3.6.7 Transmit E3 TTB-0 Register (E3, ITU-T G.832)
TxE3 TTB-0 Register (Address = 0x38)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxTTB-0[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
0
0
0
This Read/Write byte-field, along with the Tx TTB-1 through Tx TTB-15 registers permit a user to define a Trail
Access Point Identifier sequence of bytes, that will be transmitted to the Remote Terminal. The Remote
Receiving Terminal will use this sequence of bytes to verify that it is connected to the proper Transmitting
Terminal. The Transmit DS3/E3 Framer block will take the contents of these 16 registers, and insert them into
the TR byte of the outbound E3 frame. In the first of a set of 16 E3 Frames, the Transmit DS3/E3 Framer block
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