XRT72L50 Datasheet, PDF (131/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
The Framer offers a Loss of Clock (LOC) protection feature that allows the Microprocessor Interface section to
at least complete or terminate an in-process Read or Write cycle (with the local µP) should this Loss of Clock
event occur. The LOC circuitry consists of a ring oscillator that continuously checks for signal transitions at the
TxInClk[n] and RxLineClk[n] input pins. If a Loss of Clock Signal event occur such that no transitions are
occurring on these pins, then the LOC circuitry will automatically assert the RDY_DTCK signal in order to
complete (or terminate) the current Read or Write cycle with the Framer Microprocessor Interface section.
The user may enable or disable this LOC Protection feature by writing to Framer I/O Control Register, Bit 7
(Disable TxLOC), as depicted below.
Framer I/O Control Register (Address = 0x01)
BIT 7
TxLOC
Disable
R/W
1
BIT 6
LOC
R/W
0
BIT 5
Disable
RxLOc
R/W
1
BIT 4
AMI/Zero Sup
R/W
0
BIT 3
Unipolar/
Bipolar
R/W
0
BIT 2
TxLine
Clk Invert
R/W
0
BIT 1
RxLine
Clk Invert
R/W
0
BIT 0
Reframe
R/W
0
Writing a "1" to this bit-field disables the TxLOC Protection feature. Writing a "0" to this bit-field disables this
feature.
NOTE: The Ring Oscillator can be a source of noise, within the Framer chip. Hence, there may be situations where the user
will wish to disable the LOC Protection feature.
2.5 Using the PMON Holding Register
The Microprocessor Interface section consists of an 8-bit bi-directional data bus. As a consequence, the local
µP will be able to read from and write to the Framer on-chip registers, 8 bit per (read or write) cycle. Since
most of the Framer on-chip registers contain 8-bits, communicating with the local µP over an 8-bit data bus is
not much of an inconvenience. However, all of the PMON registers contain 16 bits. Consequently, any reads
of the PMON registers, will require two read cycles. To make matters potentially more complicated, these
PMON registers are Reset-upon-Read registers. Therefore, the contents of both the MSB and LSB registers
(of the READ PMON register) are reset to zero upon the first of these two read cycles.
Fortunately, the XRT72L50 Framer IC includes a feature that will make reading a PMON register a slightly less
complicated task. The Framer chip address space contains a Read-Only register known as the PMON Holding
register, which is located at 0x6C. Whenever the local µP reads in an 8-bit value of a given PMON registers
(e.g., either the upper-byte or the lower byte value of the PMON register), the other 8-bit value of that PMON
register will automatically be loaded into the PMON Holding register. As a consequence, the other 8-bit value
of the PMON register is accessible by reading the PMON Holding register.
Hence, anytime the local µP is trying to read in the contents of a PMON register, the first read access must be
made directly to one of the 8-bit values of the PMON registers (e.g., for example: the PMON LCV Event Count
Register - MSB, Address = 0x50). However, the second read must always be made to a constant location in
system memory, the PMON Holding Register.
2.6 The Interrupt Structure within the Framer Microprocessor Interface Section
The XRT72L50 Framer is equipped with a sophisticated Interrupt Servicing Structure. This Interrupt Structure
includes an Interrupt Request output, Int, numerous Interrupt Enable Registers and numerous Interrupt Status
Registers. The Interrupt Servicing Structure, within each of the three channels contains two levels of
hierarchy. The top level is at the functional block level (e.g., the Receive Section, the Transmit Section, etc.).
The lower hierarchical level is at the individual interrupt or source level. Each hierarchical level consists of a
complete set of Interrupt Status Registers/bits and Interrupt Enable Registers/bits, as will be discussed below.
Both of the functional sections, within each channel, are capable of generating Interrupt Requests to the local
µP/µC. The Framer Interrupt Structure has been carefully designed to allow the user to quickly determine the
exact source of the interrupt (with minimal latency) which will aid the local µP/µC in determining which interrupt
service routine to call up in order to respond to or eliminate the condition(s) causing the interrupt.
118