XRT72L50 Datasheet, PDF (14/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
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Figure 176. Interfacing the XRT72L50 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU ............................................ 396
Figure 177. Illustration of AMI Line Code .................................................................................................................... 397
Figure 178. Illustration of two examples of HDB3 Decoding ....................................................................................... 398
TABLE 81: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER, AND THE
SAMPLING EDGE OF THE RXLINECLK SIGNAL ................................................................................................... 399
Figure 179. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the rising edge of RxLineClk .................................................................................................... 399
Figure 180. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the falling edge of RxLineClk ................................................................................................... 399
6.3.2 The Receive E3 Framer Block ............................................................................................................... 400
6.3.2.1 The Framing Acquisition Mode ................................................................................................... 400
Figure 181. The Receive E3 Framer Block and the Associated Paths to Other Functional Blocks ............................ 400
Figure 182. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance Algorithm . 401
Figure 183. Illustration of the E3, ITU-T G.832 Framing Format ................................................................................. 402
6.3.2.2 The Framing Maintenance Mode ................................................................................................ 404
6.3.2.3 Forcing a Reframe via Software Command ................................................................................ 405
6.3.2.4 Performance Monitoring of the Frame Synchronization Section, within the Receive E3 Framer block
406
6.3.2.5 The RxOOF and RxLOF output pin. ............................................................................................ 406
6.3.2.6 E3 Receive Alarms ...................................................................................................................... 406
TABLE 82: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE FRAMING STATE
OF THE RECEIVE E3 FRAMER BLOCK ............................................................................................................... 406
6.3.2.7 Error Checking of the Incoming E3 Frames ................................................................................ 410
Figure 184. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote Terminal) with a
correct EM Byte. .......................................................................................................................................... 411
Figure 185. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote Terminal) with the
FEBE bit (within the MA byte-field) set to “0” ............................................................................................... 411
Figure 186. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote Terminal) with an
incorrect EM Byte. ....................................................................................................................................... 412
Figure 187. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote Terminal) with the
FEBE bit (within the MA byte-field) set to “1” ............................................................................................... 413
6.3.2.8 Processing of the Far-End-Block Error (FEBE) Bit-fields ............................................................ 414
6.3.2.9 Receiving the Trail Trace Buffer Messages ................................................................................ 415
6.3.3 The Receive HDLC Controller Block ..................................................................................................... 415
Figure 188. LAPD Message Frame Format ................................................................................................................ 416
TABLE 83: THE RELATIONSHIP BETWEEN THE CONTENTS OF RXLAPDTYPE[1:0] BIT-FIELDS AND THE PMDL MESSAGE TYPE/SIZE
420
6.3.4 The Receive Overhead Data Output Interface ...................................................................................... 422
Figure 189. Flow Chart depicting the Functionality of the LAPD Receiver ................................................................. 422
6.3.4.1 Method 1 - Using the RxOHClk Clock signal ............................................................................... 423
Figure 190. The Receive Overhead Output Interface block ........................................................................................ 423
Figure 191. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface (Method 1) . 424
TABLE 84: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
424
TABLE 85: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXOHFRAME WAS LAST
SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN .................... 425
6.3.4.2 Method 2 - Using RxOutClk and the RxOHEnable signals ......................................................... 427
Figure 192. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method 1). ..... 427
TABLE 86: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
(METHOD 2) .................................................................................................................................................. 428
Figure 193. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface (Method 2) . 428
TABLE 87: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES (SINCE RXOHFRAME WAS LAST SAMPLED
"HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN ................................... 429
6.3.5 The Receive Payload Data Output Interface ......................................................................................... 431
Figure 194. Illustration of the signals that are output via the Receive Overhead Data Output Interface block (for Method 2).
431
Figure 195. The Receive Payload Data Output Interface block .................................................................................. 431
TABLE 88: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK
432
6.3.5.1 Serial Mode Operation Behavior of the XRT72L50 ..................................................................... 433
Figure 196. The Terminal Equipment being interfaced to the Receive Payload Data Input Interface Block (Serial Mode
Operation) .................................................................................................................................................... 433
6.3.5.2 Nibble-Parallel Mode OperationBehavior of the XRT72L50 ........................................................ 434
Figure 197. An Illustration of the behavior of the signals between the Receive Payload Data Output Interface block of the
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