XRT72L50 Datasheet, PDF (210/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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PMON Framing Bit Error Event Count Register - LSB (Address = 0x53)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
F-Bit Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
When the µP/µC reads these registers, it will read in the number of framing bit errors that have been detected
since the last read of these two registers. These registers are reset upon read.
4.3.2.5 DS3 Receive Alarms
The Receive DS3 Framer block is capable of detecting any of the following alarm conditions.
• LOS (Loss of Signal)
• AIS (Alarm Indication Signal)
• The Idle Pattern.
• FERF (Far-End Receive Failure) of Yellow Alarm condition.
• FEBE (Far-End-Block Error)
• Change in AIC State
The methods by which the Receive DS3 Framer block uses to detect and declare each of these alarm
conditions are described below.
4.3.2.5.1
The Loss of Signal (LOS) Alarm
The Receive DS3 Framer block will declare a Loss of Signal (LOS) state when it detects 180 consecutive
incoming “0s” via the RxPOS and RxNEG input pins OR if the RLOS input pin (of the XRT73L00 DS3 LIU IC) is
asserted (e.g., driven "High" and conneted to the ExtLOS pin78, of the Framer IC). The Receive DS3 Framer
block will indicate the occurrence of an LOS condition by:
1. Asserting the RxLOS output pin (e.g., toggles it "High").
2. Setting Bit 6 (RxLOS) within the Rx DS3 Configuration and Status Register to 1, as depicted below.
NOTE: LOS is always declared if the RLOS input is driven “High”. The 180 consecutive “zero” pulse internal LOS criteria
can be disabled by setting bit 5 at 0x00 to “0”
Rx DS3 Configuration and Status Register, (Address = 0x10)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RxAIS
RxLOS
RxIdle
RxOOF
Reserved
RO
RO
RO
RO
RO
0
1
0
1
x
BIT2
Framing on
Parity
R/W
x
BIT 1
BIT 0
F-Sync Algo M-Sync Algo
R/W
R/W
x
x
3. The Receive DS3 Framer block will generate a Change in LOS Status interrupt request.
NOTE: The Receive DS3 Framer will also declare an OOF condition and perform all of the notification procedures as
described in Section 4.3.2.2.
4. Force the on-chip Transmit Section to transmit a FERF (Far-End Receive Failure) indicator back out to the
remote terminal.
The Receive DS3 Framer block will clear the LOS condition when at least 60 out of 180 consecutive received
bits are 1.
NOTE: The Receive DS3 Framer block will also generate the Change in LOS Condition interrupt, when it clears the LOS
Condition.
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