XRT72L50 Datasheet, PDF (143/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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UDL = User Data Link
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE 29. DS3 FRAME FORMAT FOR M13
X
I
F1
I C11 I
F0
I C12 I
F0
I C13 I
F1
I
I
X
I
F1
I C21 I
F0
I C22 I
F0
I C23 I
F1
I
P
I
F1
I C31 I
F0
I C32 I
F0
I C33 I
F1
I
P
I
F1
I C41 I
F0
I C42 I
F0
I C43 I
F1
I
M0
I
F1
I C51 I
F0
I C52 I
F0
I C53 I
F1
I
M1
I
F1
I C61 I
F0
I C62 I
F0
I C63 I
F1
I
M0
I
F1
I C71 I
F0
I C72 I
F0
I C73 I
F1
I
X = Signaling bit for network control
I = Payload Information (84 bit packets)
Fi = Frame synchronization bit with logic value i
Cij = jth stuff code bit of ith channel
P = Parity bit
Mi = multiframe synchronization bit with logic values i
To choose between these two frame formats, write the appropriate data to bit 2 of the Framer Operating Mode
Register (Address = 0x00), as depicted below.
This bit setting configures the frame format for both the Transmit and Receive Section of the XRT72L50..
Framer Operating Mode Register (Address = 0x00)
BIT 7
BIT 6
BIT 5
BIT 4
Local Loop-back DS3/E3 Internal LOS RESET
Enable
R/W
R/W
R/W
R/W
x
1
x
0
BIT 3
Interrupt
Enable Reset
R/W
x
BIT2
Frame Format
R/W
x
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
x
x
TABLE 13: BIT 2 SETTING WITHIN THE FRAMER OPERATING MODE REGISTER AND THE RESULTING DS3 FRAMING
FORMAT
BIT 2
0
1
DS3 FRAME FORMAT
C-Bit Parity
M13
Each of the two DS3 Frame Formats, as presented in Figure 28 and Figure 29, constitute an M-frame or a full
DS3 Frame. Each M-frame consists of 7 - 680 bit F-frames, sometimes referred to as subframes. Each F-
frame is represented by the individual rows of payload and overhead bits and can be further divided into 8
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