XRT72L50 Datasheet, PDF (397/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE 75: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TX AIS ENABLE) WITHIN THE TX E3
CONFIGURATION REGISTER, AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION
BIT 2
0
1
TRANSMIT E3 FRAMER'S ACTION
Normal Operation:
The Transmit Section of the XRT72L50 Framer IC will transmit E3 traffic based upon data that it accepts via
the Transmit Payload Data Input Interface block, the Transmit Overhead Data Input Interface block, the Trans-
mit HDLC Controller block and internally generated overhead bytes.
Transmit AIS Pattern:
The Transmit E3 Framer block will overwrite the E3 traffic, within an Unframed All Ones pattern.
NOTE: This bit is ignored whenever the TxLOS bit-field is set.
6.2.4.2.1.2
Transmit LOS Enable - Bit 1
This read/write bit field allows the user to transmit an LOS (Loss of Signal) pattern to the remote terminal, upon
software control. Table 76 relates the contents of this bit field to the Transmit E3 Framer block's action.
TABLE 76: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (TX LOS) WITHIN THE TX E3 CONFIGURATION
REGISTER, AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION
BIT 1
0
1
TRANSMIT E3 FRAMER'S ACTION
Normal Operation:
The Overhead bits are either internally generated, or they are inserted via the Transmit Overhead Data Input
Interface or the Transmit HDLC Controller blocks. The Payload bits are received from the Transmit Payload
Data Input Interface.
Transmit LOS Pattern:
When this command is invoked the Transmit E3 Framer will do the following.
• Set all of the overhead bytes to "0" (including the FA1 and FA2 bytes)
Overwrite the E3 payload bits with an "all zeros" pattern.
NOTE: When this bit is set, it overrides all of the other bits in this register.
6.2.4.2.1.3
Transmitting FEBE (Far-End Block Error) and FERF (Far-End Receive Failures) indicators
via Software control
The "TxE3 Configuration" register (Address = 0x30) contains a register bit (Bit 0 - TxMARx) that permits the
user to control the state of the FEBE and FERF bit-fields, in the outbound E3 data stream.
The bit-format of the "TxE3 Configuration" register is presented below.
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
TxDL in NR
R/W
0
BIT 3
Not Used
BIT 2
TxAIS Enable
RO
R/W
0
0
BIT 1
TxLOS
Enable
R/W
0
BIT 0
TxMARx
R/W
0
This read/write bit-field permits the user to configure the XRT72L50 to do one of the following.
A. Set the "FEBE" and "FERF" bit-fields (within the MA byte of "outbound" E3 frames) to the appropriate state
based upon conditions detected by the "Receive DS3/E3 Framer" block.
B. To (via software-control) set the states of the "FEBE" and "FERF" bit-fields (within the MA byte of "out-
bound" E3 frames).
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