XRT72L50 Datasheet, PDF (69/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Bit 3 - FERF Interrupt Enable
This Read/Write bit-field is used to enable or disable the Change in FERF (Far End Receive Failure) Status
interrupt. Setting this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on Far-End Receive Failures (or Yellow Alarms), refer to Section 4.3.2.5.4.
Bit 2 - AIC Interrupt Enable
This Read/Write bit field allows the user to enable or disable the Change in AIC value interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on this interrupt condition, refer to Section 4.3.2.5.6.
Bit 1 - OOF Interrupt Enable
This Read/Write bit field is used to enable or disable the Change in Out-of-Frame (OOF) status interrupt.
Setting this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the OOF Condition, refer to Section 4.3.2.2.
Bit 0 - P-Bit Error Interrupt Enable
This Read/Write bit-field is used to enable or disable the Detection of P-Bit Error interrupt. Setting this bit-field
to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the P-Bit Error Checking/Detection, refer to Section 4.3.2.6.1.
2.3.2.11 Receive DS3 Interrupt Status Register
RxDS3 Interrupt Status Register (Address = 0x13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
Idle Interrupt
Status
FERF
Interrupt
Status
AIC
Interrupt
Status
OOF
Interrupt
Status
P-Bit Error
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
1
0
0
0
0
0
0
Bit 7 - CP Bit Error Interrupt Status
This Reset-upon-Read bit-field indicates whether or not the Detection of CP Bit Error Interrupt has occurred
since the last read of this register. This bit-field will be “0” if the Detection of CP-Bit Error Interrupt has not
occurred since the last read of this register. Conversely, this bit-field will be set to “1” if this interrupt has
occurred since the last read of this register. The Detection of CP Bit Error Interrupt will occur if the Receive
DS3/E3 Framer block detects a CP bit-error in the incoming DS3 frame.
NOTE: This bit-field is only valid if the channel has been configured to operate in the DS3, C-bit Parity Framing format.
Bit 6 - LOS Interrupt Status
This Reset Upon Read bit will be set to "1", if the Receive DS3/E3 Framer block has detected a Change in the
LOS Status condition, since the last time this register was read. This bit-field will be asserted under either of
the following conditions:
For DS3 Applications
1. When the Receive DS3/E3 Framer block detects the occurrence of an LOS Condition (e.g., the occurrence
of 180 consecutive spaces in the incoming DS3 data stream), and
2. When the Receive DS3/E3 Framer block detects the end of an LOS Condition (e.g., when the Receive DS3
Framer detects 60 mark pulses in the last 180 bit periods).
NOTE: For more information in the LOS of Signal (LOS) Alarm, refer to Section 4.3.2.5.1.
Bit 5 - AIS Interrupt Status
This Reset Upon Read bit field will be set to "1", if the Receive DS3/E3 Framer block has detected a Change in
the AIS condition, since the last time this register was read. This bit-field will be asserted under either of the
following two conditions:
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