XRT72L50 Datasheet, PDF (177/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Transmit FEAC Processor will generate an interrupt (if enabled) to the local µP/µC upon completion of the 10th
transmission of the FEAC Message. The purpose of having the Framer generate this interrupt is to let the local
µP/µC know that the Transmit FEAC Processor is now available and ready to transmit a new FEAC message.
The Transmit FEAC Processor continues to send the FEAC Code Message even after the 10^th transmission
until the TxFEAC processor is disabled or a new FEAC code transmission is initiated.
If the TxFEAC processor is disabled, the FEAC bit contains a “1” which the remote Rx side interprets as an idle
FEAC message.
Figure 49 presents a flow chart depicting how to use the Transmit FEAC Processor.
NOTE: The FEAC processor starts transmitting the last FEAC message when enabled. Execute the “Initiate Transmission
of the Outbound FEAC Message” step without delay to prevent unintended incorrect transmission. Rx FEAC
prossecor validates a FEAC code upon receiving the same code 8 times.
FIGURE 49. A FLOW CHART DEPICTING HOW TO TRANSMIT A FEAC MESSAGE VIA THE FEAC TRANSMITTER
START
1
W riteSix-Bit O utbound FEAC Value Into
the TxDS3 FEAC Register
T he address is located at 0x32.
Enable the Transm it FEAC Processor
T his is accom plished by writing xxxxx1xx
into the T xDS3 FEAC Configuration and
Status Register.
NOTE:
The FEAC processor starts transm itting
the last FEAC m essage w hen enabled.
Execute the “Initiate Transm ission of
the Outbound FEAC M essage” step
w ithout delay to prevent unintended
incorrect transm ission. Rx FEAC
prossecor validates a FEAC code upon
receiving the sam e code 8 tim es.
Initiate Transm ission of the outbound
FEAC M essage
T his is accom plished by writing xxxxx1xx
into the T xDS3 FEAC Configuration and
Status Register.
T ransm it FEAC Processor Encapsulates the O utbound
FEAC value into a 16 bit Fram ing Structure.
T ransm it FEAC Processor Proceeds to Insert the 16 bit
M essage (in a bit-by-bit M anner) into the FEAC Fields
of each outbound DS3 Fram e.
Has the
NO ^{16-bit FEAC Mesage} YES
been transm itted to
the rem ote term inal
10 tim es ?
Is T ransm ission
of the 16-bit
FEAC Message
com plete?
YES
NO
Generate the Transm it FEAC Interrupt
Invoke the Transm it FEAC Interrupt
Service Routine
1
NOTE: For a detailed description of the Receive FEAC Processor within the Receive DS3 HDLC Controller block, please
see Section 4.3.3.1.
4.2.3.2 Message-Oriented Signaling (e.g., LAP-D) processing via the Transmit DS3 HDLC
Controller
The LAPD Transmitter within the Transmit DS3 HDLC Controller Block allows the user to transmit Path
Maintenance Data Link (PMDL) messages to the remote terminal via the outbound DS3 Frames. The
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