XRT72L50 Datasheet, PDF (62/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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Setting this bit-field to "0" configures the XRT72L50 to transmit and receive data via a Zero-Suppression line
code.
Setting this bit-field to "1" configures the XRT72L50 to transmit and receive data via the Alternate Mark
Inversion line code.
If the XRT72L50 is configured to transmit and receive data using a Zero-Suppression code while operating in
the DS3 Mode, then the chip will transmit and receive data using the B3ZS Line Code.
If the XRT72L50 is configured to transmit and receive data using a Zero-Suppression code while operating in
the E3 Mode, then the chip will transmit and receive data using the HDB3 Line Code.
This bit-field will be ignored if bit 3 (Unipolar/Bipolar) of this Register is set to "1" (Unipolar Mode).
Bit 3 - Unipolar/Bipolar
This Read/Write bit-field permits the user to configure the XRT72L50 to transmit and receive data from an LIU
IC, in either the Single-Rail or Dual-Rail format.
Setting this bit-field to "0" configures the XRT72L50 to operate in the Bipolar or Dual-Rail Format. In this mode,
the Transmit Section of the XRT72L50 will output data to the LIU via both the TxPOS and TxNEG output pins.
The Receive Section of the device will receive data from the LIU via both the RxPOS and RxNEG output pins.
Setting this bit-field to "1" configures the XRT72L50 to operate in the Unipolar or Single-Rail Format. In this
mode, the Transmit Section of the XRT72L50 will output data to the LIU in a binary data stream manner via the
TxPOS output pin. The Receive Section of the device will receive data from the LIU in a binary data stream
manner via the RxPOS input pin.
NOTE: For more information on the transmission and reception of data in the Single-Rail or Dual-Rail format, refer to
Section 4.2.5.
Bit 2 - TxLineClk Invert
This Read/Write bit-field permits the user to configure the XRT72L50 to output data via the TxPOS and TxNEG
output pins on the rising or falling edge of TxLineClk.
Setting this bit-field to "0" configures the XRT72L50 to output data, via the TxPOS and TxNEG output pins, on
the rising edge of TxLineClk.
Setting this bit-field to "1" configures the XRT72L50 to output data, via the TxPOS and TxNEG output pins, on
the falling edge of TxLineClk.
Bit 1 - RxLineClk Invert
This Read/Write bit-field permits the user to configure the XRT72L50 to latch data on the RxPOS and RxNEG
input pins on the rising or falling edge of RxLineClk.
Setting this bit-field to "0" configures the XRT72L50 to latch the data on the RxPOS and RxNEG input pins, into
the device, on the rising edge of RxLineClk.
Setting this bit-field to "1" configures the XRT72L50 to latch the data on the RxPOS and RxNEG input pins, into
the device, data, on the falling edge of RxLineClk.
Bit 0 - Reframe
This Read/Write bit-field permits the user to configure the Receive Section of the XRT72L50 to start a new
frame search. A "0" to "1" transition in this bit-field will force the device to start a new frame search. The bit
should be reset to “0” after the transistion to prevent a continous forced reframing condition.
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