XRT72L50 Datasheet, PDF (61/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Bits 1 & 0 - TimRefSel[1:0] - Timing Reference Select
These two Read/Write bit-fields permits the user to select both a Framing Reference and Timing Reference for
the Transmit Section of the XRT72L50. The following table relates the states of these two bit-fields to the
selected Framing and Timing references.
TIMREFSEL[1:0]
FRAMING
REFERENCE
TIMING REFERENCE
00
Asynchronous RxLineClk Input Signal
01
TxFrameRef TxInClk Input Signal
10
Asynchronous TxInClk Input Signal
11
Asynchronous TxInClk Input Signal
NOTE: For more information on Framing and Timing References, refer to Section 4.2.
2.3.2.2 I/O Control Register
NOTE: Data can be transmitted in;
a. Unipolar
b. Bipolar with AMI, or
c. Bipolar with AMI and B3ZS (for DS3)/HDB3 (for E3)
I/O Control Register (Address = 0x01)
BIT 7
Disable
TxLOC
R/W
1
BIT 6
LOC
RO
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/
ZeroSup
BIT 3
Unipolar/
Bipolar
R/W
R/W
0
0
BIT 2
TxLine
Clk
Invert
R/W
0
BIT 1
RxLine
Clk
Invert
R/W
0
BIT 0
Reframe
R/W
0
Bit 7 - DisableTxLOC
This Read/Write bit-field permits the user to enable or disable the Transmit Loss of Clock feature.
Setting this bit-field to "0" enables the Transmit Loss of Clock feature. Conversely, setting this bit-field to "1"
disables the Transmit Loss of Clock feature.
NOTE: For more details into the Transmit Loss of Clock feature, refer to Section 2.4.
Bit 6 - LOC (Loss of Clock) Status
This Read-Only bit-field reflects the Loss of Clock status for the XRT72L50. The XRT72L50 will set this bit-
field to "0" under normal operation conditions. Conversely, if the XRT72L50 experiences a Loss of Clock event,
then it will set this bit-field to "1".
NOTE: For more details into the Loss of Clock status, refer to Section 2.4.
Bit 5 - DisableRxLOC
This Read/Write bit-field permits the user to enable or disable the Receive Loss of Clock feature.
Setting this bit-field to "0" enables the Receive Loss of Clock feature. Conversely, setting this bit-field to "1"
disables the Receive Loss of Clock feature.
NOTE: For more details into the Receive Loss of Clock feature, refer to Section 2.4.
Bit 4 - AMI/ZeroSup
This Read/Write bit-field permits the user to configure the XRT72L50 to transmit and receive data via the AMI
(Alternate Mark Inversion) line code or via a Zero-Suppression (e.g, B3ZS/HDB3) line code.
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