XRT72L50 Datasheet, PDF (136/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
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executing this one interrupt service routine. Consequently, the local Microprocessor/Microcontroller (along with
portions of the overall system) now becomes non-functional.
In order to prevent this phenomenon from ever occuring, the Framer IC allows the user to automatically reset
the interrupt enable bits, following their activation. The user can implement this feature by writing the
appropriate value into Bit 3 (Interrupt Enable Reset) within the Framer Operating Mode register, as illustrated
below.
BIT 7
Local
Loop-Back
R/W
0
BIT 6
DS3/E3
R/W
0
BIT 5
Internal
LOS Enable
R/W
1
BIT 4
RESET
R/W
0
BIT 3
BIT 2
Interrupt Frame Format
Enable Reset
R/W
R/W
1
0
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
1
1
Writing a “1” to this bit-field configures the Framer to automatically disable a given interrupt, following its
activation. Writing a “0” to this bit-field configures the Framer to leave the Interrupt Enable bit as is, following
interrupt activation.
If a user opts to implement the Automatic Reset of Interrupt Enable Bits feature, then he/she might wish to
configure the Microprocessor/Microcontroller to go back and re-enable these interrupts at a later time.
2.6.2 One-Second Interrupts
The Block Interrupt Status register, and Block Interrupt Enable register each contain a bit-field for the One-
Second Interrupt. If this interrupt is enabled (within the Block Interrupt Enable register), then the Framer will
automatically generate an interrupt request to the Microprocessor/Microcontroller repeatedly at one-second
intervals. At a minimum, the user’s interrupt service routine must service this interrupt by reading the Block
Interrupt Status register (Address = 0x05). Once the Microprocessor/Microcontroller has read this register,
then the following things will happen.
1. The One-Second Interrupt bit-field, within the Block Interrupt Status register, will be reset to “0”.
2. The Framer will negate the Int (Interrupt Request) output pin.
The purpose of providing this One-Second interrupt is to allow the Microprocessor/Microcontroller the
opportunity to perform certain tasks at One-Second intervals. The user can accomplish this by including the
necessary code (for these various tasks) as a part of the interrupt service routine, for the One-Second type
interrupt. Some of these tasks could include:
• Reading in the contents of the One-Second Performance Monitor registers.
• Reading various other Performance Monitor registers.
• Writing a new PMDL Message into the Transmit LAPD Message buffer. After the LAPD Transmitter has been
enabled and commanded to initiate transmission of the LAPD Message frame (containing the PMDL
Message, residing within the Transmit LAPD Message buffer), the LAPD Transmitter will continue to re-
transmit this same LAPD Message frame, repeatedly at One-Second intervals, until it has been disabled. If a
new PMDL message is written into the Transmit LAPD Message buffer immediately following the occurrence
of a One-Second Interrupt, then this will ensure that this Write activity will not interfere with this periodic
transmission of the LAPD Message frames.
Notes regarding the Block Interrupt Enable and Block Interrupt Status Registers:
1. The Block Interrupt Enable Register allows the user to globally disable all potential interrupts within either
the Transmit or Receive sections, by writing a “0” into the appropriate bit-field of this register. However, the
Block Interrupt Enable register does not allow the user to globally enable all potential interrupts within a
given functional block. In other words, enabling a given functional block does not automatically enable all
of its potential interrupt sources. Those potential interrupt sources that have been disabled at the source
level will remain disabled, independent of the status of their associated functional blocks.
2. The Block Interrupt Enable register is set to 0x00 upon power or reset. Therefore, the user will have to
write some “1’s” into this register, in order to enable some of the interrupts.
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