XRT72L50 Datasheet, PDF (36/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
áç
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
t₂₇ TxInClk clock (rising edge) to TxOHIns hold-time
0
0
MAX.
UNITS
CONDITIONS
ns DS3 Applications
ns E3, ITU-T G.832
Applications
0
t₂₈ TXOH to TxInClk (rising edge) set-up Time
254
72
ns E3, ITU-T G.751
Applications
ns DS3 Applications
ns E3, ITU-T G.832
Applications
15
t₂₉ TxInClk clock (rising edge) to TxOH hold-time
0
0
ns E3, ITU-T G.751
Applications
ns DS3 Applications
ns E3, ITU-T G.832
Applications
0
ns
t_29A TxOHEnable to TxOHIns/TxOH Delay
1
Transmit LIU Interface Timing (see Figure 9 and Figure 10)
t₃₁ Rising or falling edge of TxLineClk to rising edge of
TxPOS or TxNEG
ns
2.4
ns
t₃₂ Period of TxLineClk
22.36
ns
29.10
ns
t₃₃ RxPOS, RxNEG hold time from rising edge of TxLn- 3
ns
Clk
Receive LIU Interface Timing (see Figure 11 and Figure 12)
t₃₈ RxPOS or RxNEG set-up time to rising edge or fall-
0
ns
ing edge of RxLineClk.
t₃₉ RxPOS or RxNEG hold time, from rising edge or fall- 4
ns
ing edge of RxLineClk
(Framer is configured to sample data on RxPOS and
RxNEG input pins on the rising edge of RxLineClk)
t₄₂ Period of RxLineClk
22.36
ns
29.10
ns
Receive Payload Data Output Interface Timing - Serial Mode Operation (See Figure 13)
t₅₀ Rising edge of RxClk to Payload Data (RxSer) out-
put delay
13
ns
16
ns
E3, ITU-T G.751
Applications
DS3 Applications
E3 Applications
DS3 Applications
E3 Applications
DS3 Applications
E3 Applications
23