XRT72L50 Datasheet, PDF (137/471 Pages) Exar Corporation – SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
The remaining registers, listed in Table 9, Table 10 and Table 11 will be presented in the discussion of the
functional blocks, within the XRT72L50 Framer IC. These discussions will present more details about the
interrupt causes and how to properly service. them.
3.0 THE LINE INTERFACE AND SCAN SECTION
The Line Interface and Scan Section of the XRT72L50 DS3/E3 Framer IC consists of 5 output pins, 3 input
pins, a Read/Write register, and a Read-Only register.
The purpose of the Line Interface Drive and Scan section is to permit the user to monitor and exercise control
over many aspects of the XRT73L0x DS3/E3/STS-1 LIU IC without having to develop the necessary off-chip
glue-logic.
Figure 27 presents a simple circuit schematic that depicts how the XRT72L50 DS3/E3 Framer IC could be
interfaced to the XRT73L0x DS3/E3/STS-1 LIU IC.
FIGURE 27. XRT72L50 DS3/E3 FRAMER INTERFACED TO THE XRT73L0X DS3/E3/STS-1 LIU
TxS E R
TxInClk
TxFram e
N IB INT F
RESETB
INTB
CSB
RW
DS
AS
INTB
A [8 :0 ]
D [7 :0 ]
VDD
R xS e r
R xC lk
RxFram e
RxLO S
RxO O F
RxRE D
R xA I S
U1
45
43 ^TxSer/SndMsg
61 ^TxInClk
TxFram e
25
N ib b le In tf
28
R eset
13
8 ^Int
7 ^CS
10 ^{W R_R/W}
9 ^RD_DS
6 ^ALE_AS
RDY_DTCK
15
16 ^A0
17 ^A1
18 ^A2
19 ^A3
20 ^A4
21 ^A5
22 ^A6
23 ^A7
A8
32
33 ^D0
34 ^D1
35 ^D2
36 ^D3
37 ^D4
38 ^D5
39 ^D6
D7
27
MOTO
86
88 ^RxSer/RxIdle
90
R xC lk
RxFram e
95
94
RxLO S
93
RxO O F
87
RxRE D
R xA I S
XRT72L50
65
TxPOS
64
TxNE G
63
T xL in eC lk
79
DMO
78
E xtLO S
77
RLOL
69
LLOOP
70
RLOOP
68
TAOS
67
TxLev
66
E nc oD is
71
R eq
U2
37
TPDATA
38
TNDATA
36
TCLK
4
DMO
24
RLOS
23
RLOL
14
LLB
15
RLB
2
TAOS
1
TxLE V
21
E NC O D IS
12
REQDIS
76
RxPO S
75
RxNE G
74
R xL in eC lk
33
RPOS
32
RNEG
31
RCLK1
XRT73L00
41
TTIP
40
TRING
44
MTIP
43
M R IN G
1 ^R3 2
270
1 ^R4 2
270
R1
1
2
36
T
11 5
R2
1
2
36
4
8
1:
1
TTIP
TRING
8
RTIP
9
RRING
C1
1
2
0.01uF
R5
37.5
R6
37.5
1 ^T2 5
4
8
1:1
RTIP
RRING
3.1 Bit-Fields within the Line Interface Drive Register
As mentioned above, the Line Interface Drive and Scan section consists of five output pins and three input
pins. The logic state of the output pins are controlled by the contents within the Line Interface Drive register, as
depicted below.
LINE INTERFACE DRIVE Register (Address = 0x80)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
ILOOP
Not Used
REQB
TAOS
ENCODIS
R/W
RO
R/W
R/W
R/W
0
0
0
0
1
BIT 2
TxLEV
R/W
0
BIT 1
RLOOP
R/W
0
BIT 0
LLOOP
R/W
0
124